Inventor

LING ZICHENG GARY

US16 patents

⚠️ This page may combine multiple inventors who share the name “LING ZICHENG GARY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADVANCED MICRO DEVICES INC

12 patents

US6153455ANov 28, 2000

Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer

ADVANCED MICRO DEVICES INC63 citations94

US6479350B1Nov 12, 2002

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

ADVANCED MICRO DEVICES INC46 citations92

US6306702B1Oct 23, 2001

Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length

ADVANCED MICRO DEVICES INC29 citations92

US6287904B1Sep 11, 2001

Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer

ADVANCED MICRO DEVICES INC23 citations90

US6265253B1Jul 24, 2001

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

ADVANCED MICRO DEVICES INC14 citations74

US6368762B1Apr 9, 2002

Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation

ADVANCED MICRO DEVICES INC7 citations73

US6214655B1Apr 10, 2001

Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation

ADVANCED MICRO DEVICES INC8 citations73

US6482573B1Nov 19, 2002

Exposure correction based on reflective index for photolithographic process control

ADVANCED MICRO DEVICES INC8 citations72

US6221706B1Apr 24, 2001

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

ADVANCED MICRO DEVICES INC6 citations63

XILINX INC

4 patents

US6784685B2Aug 31, 2004

Testing vias and contacts in an integrated circuit

XILINX INC40 citations93

US6503765B1Jan 7, 2003

Testing vias and contacts in integrated circuit fabrication

XILINX INC29 citations89

US6868537B1Mar 15, 2005

Method of generating an IC mask using a reduced database

XILINX INC14 citations82

US7046026B2May 16, 2006

Testing vias and contracts in integrated circuit

XILINX INC5 citations70

LING ZICHENG GARY

ADVANCED MICRO DEVICES INC

Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length

Two step mask process to eliminate gate end cap shortening

Nitride disposable spacer to reduce mask count in CMOS transistor formation

Nitride disposable spacer to reduce mask count in CMOS transistor formation

Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation

Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation

Exposure correction based on reflective index for photolithographic process control

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

XILINX INC

Testing vias and contacts in an integrated circuit

Testing vias and contacts in integrated circuit fabrication

Method of generating an IC mask using a reduced database

Testing vias and contracts in integrated circuit