Inventor

CARTIER EDUARD A

US80 patents

⚠️ This page may combine multiple inventors who share the name “CARTIER EDUARD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CARTIER EDUARD A

IBM

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique

Extremely-thin silicon-on-insulator transistor with raised source/drain

Removal of charged defects from metal oxide-gate stacks

Interfacial oxidation process for high-k gate dielectric process integration

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Method for forming dielectric stack without interfacial layer

High-dielectric constant insulators for FEOL capacitors

Method to improve reliability of replacement gate device

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Deep trench (DT) metal-insulator-metal (MIM) capacitor

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Extremely-thin silicon-on-insulator transistor with raised source/drain

CMOS transistors with differential oxygen content high-k dielectrics

Deuterium reservoirs and ingress paths

Low threshold voltage semiconductor device with dual threshold voltage control means

Method of forming metal/high-k gate stacks with high mobility

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Method to improve reliability of replacement gate device

FinFET structure and method to adjust threshold voltage in a FinFET structure

CMOS transistors with differential oxygen content high-K dielectrics

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Low threshold voltage semiconductor device with dual threshold voltage control means

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

Method of forming gate stack for semiconductor electronic device

Dielectric stack without interfacial layer

High-dielectric constant insulators for FEOL capacitors

Fast recrystallization of hafnium or zirconium based oxides in insulator-metal structures

Method to improve reliability of high-K metal gate stacks

Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures

Deuterium reservoirs and ingress paths

Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby

MOS device having a passivated semiconductor-dielectric interface

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement

Method to improve reliability of replacement gate device

Method of restoring a flash memory in an integrated circuit chip package by addition of heat and an electric field

FinFET structure and method to adjust threshold voltage in a FinFET structure

High-dielectric constant insulators for feol capacitors

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

ANDO TAKASHI

Replacement gate structure for transistor with a high-K gate stack

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device

BOJARCZUK JR NESTOR A

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

CARTIER EDUARD A

FinFET structure and method to adjust threshold voltage in a FinFET structure

GLOBALFOUNDRIES INC

Non-volatile memory device employing a deep trench capacitor

TOKYO ELECTRON LTD

Method for controlling the forming voltage in resistive random access memory devices

CAI JIN

Fabrication of devices having different interfacial oxide thickness via lateral oxidation