Inventor

JU DONG-HYUK

US44 patents

⚠️ This page may combine multiple inventors who share the name “JU DONG-HYUK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JU DONG-HYUK

ADVANCED MICRO DEVICES INC

SOI MOSFET and method of fabrication

Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer

Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

Process for fabricating a semiconductor device having assymetric source-drain extension regions

CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance

SOI device with structure for enhancing carrier recombination and method of fabricating same

SOI MOSFET having amorphized source drain and method of fabrication

Method of forming differential spacers for individual optimization of n-channel and p-channel transistors

Multi-Thickness silicide device formed by succesive spacers

Method of making a multi-thickness silicide SOI device

Polysilicon insulator material in semiconductor-on-insulator (SOI) structure

CMOS processing employing zero degree halo implant for P-channel transistor

Silicidation and deep source-drain formation prior to source-drain extension formation

Method of manufacturing a semiconductor device containing shallow LDD junctions

CMOS processing employing separate spacers for independently optimized transistor performance

Bonded SOI for floating body and metal gettering control

Fabrication of raised source-drain transistor devices

Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion

Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

High voltage transistor scaling tilt ion implant method

Method of fabricating multi-thickness silicide device formed by disposable spacers

Depleted sidewall-poly LDD transistor

SOI device with structure for enhancing carrier recombination and method of fabricating same

SOI device with body recombination region, and method

Flash memory cell having reduced leakage current

Method and circuit for measuring charge dump of an individual transistor in an SOI device

Method of manufacturing a semiconductor device having shallow junctions

Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes

CMOS semiconductor device containing N-channel transistor having shallow LDD junctions

Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile

Device and method for testing performance of silicon structures

Method for fabricating a memory device

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

Heat removal by removal of buried oxide in isolation areas

Dual SOI film thickness for body resistance control

SPANSION LLC

Method to obtain multiple gate thicknesses using in-situ gate etch mask approach

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

Junction leakage suppression in memory devices

ADVANCED MIRCO DEVICES INC

Depleted sidewall-poly LDD transistor

LIN CHUAN

Controlling the latchup effect

CYPRESS SEMICONDUCTOR CORP

Controlling the latchup effect

KHAN IMRAN

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

AHMED SHIBLY S

Junction leakage suppression in memory devices