Inventor

BERNSTEIN DEBRA

US79 patents

⚠️ This page may combine multiple inventors who share the name “BERNSTEIN DEBRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERNSTEIN DEBRA

INTEL CORP

Microengine for parallel processor architecture

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Arbitrating command requests in a parallel multi-threaded processing system

Register set used in multithreaded parallel processor architecture

Enqueueing entries in a packet queue referencing packets

Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment

Software controlled content addressable memory in a general purpose execution datapath

Mapping requests from a processing unit that uses memory-mapped input-output space

Read lock miss control and queue management

Scratchpad memory

Thread signaling in multi-threaded network processor

Parallel multi-threaded processing

Communication between processors

Handling contiguous memory references in a multi-queue system

Method and apparatus for sharing access to a bus

Read lock miss control and queue management

Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section

Scratchpad memory

Optimizations to receive packet status from fifo bus

Memory shared between processing threads

Scratchpad memory

Scratchpad memory

Thread signaling in multi-threaded processor

Breakpoint method for parallel hardware threads in multithreaded processor

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Multithreaded microprocessor with register allocation based on number of active threads

Communication between processors

Control mechanisms for enqueue and dequeue operations in a pipelined network processor

Software controlled content addressable memory in a general purpose execution datapath

Microengine for parallel processor architecture

Queue management

Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch

Bus interface with a first-in-first-out memory

Communication between processors

Enqueue operations for multi-buffer packets

Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms

Context pipelines

Command ordering

Register set used in multithreaded parallel processor architecture

Queue arrays in network devices

Data transfer mechanism using unidirectional pull bus and push bus

Processor having content addressable memory for block-based queue structures

Registers for data transfers

Branch instruction for processor with branching dependent on a specified bit in a register

Free list and ring data structure management

Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access

Folding for a multi-threaded network processor

DIGITAL EQUIPMENT CORP

Mechanism for high bandwidth DMA transfers in a PCI environment

Pipelined computer with operand context queue to simplify context-dependent execution flow

Mechanism for high bandwidth DMA transfers in a PCI environment