Inventor

AMICK BRIAN

US34 patents

⚠️ This page may combine multiple inventors who share the name “AMICK BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AMICK BRIAN

SUN MICROSYSTEMS INC

Using a push/pull buffer to improve delay locked loop performance

Chip/package resonance damping using controlled package series resistance

Design-for-test technique for a delay locked loop

Quantifying a difference between nodal voltages

Method for optimizing loop bandwidth in delay locked loops

Adjustable capacitances for DLL loop and power supply noise filters

Programmable bias-generator for self-biasing a delay locked loop

Integrated on-chip process, temperature, and voltage sensor module

Method and apparatus to store delay locked loop biasing parameters

Jitter estimation for a phase locked loop

Method for decoupling capacitor optimization for a temperature sensor design

Optimization of loop bandwidth for a phase locked loop

Circuit for post-silicon control of delay locked loop charge pump current

Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor

Post-silicon phase offset control of phase locked loop input receiver

Method and system for estimating jitter in a delay locked loop

Post-silicon control of phase locked loop charge pump current

CMOS-microprocessor chip and package anti-resonance apparatus

CMOS-microprocessor chip and package anti-resonance method

Post-silicon control of an embedded temperature sensor

Adjustment and calibration system for post-fabrication treatment of on-chip temperature sensor

Low voltage temperature-independent and temperature-dependent voltage generator

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

Phase locked loop input receiver design with delay matching feature

Method for simulating power supply noise in an on-chip temperature sensor

Reducing voltage variation in a phase locked loop

Post-silicon bias-generator control for a differential phase locked loop

Reducing PECL voltage variation

CMOS-microprocessor chip and package anti-resonance pass-band shunt apparatus

I/O interface anti-resonance passband shunting technique

Digital delay locked loop with extended phase capture range

ADVANCED MICRO DEVICES INC

Integrated controller for training memory physical layer interface

KRISHNAN GUHAN

Method and apparatus to reduce memory read latency

TALBOT GERALD R

Programmable delay module testing device and methods thereof