Inventor

LIU DEAN

US59 patents

⚠️ This page may combine multiple inventors who share the name “LIU DEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU DEAN

SUN MICROSYSTEMS INC

Using a push/pull buffer to improve delay locked loop performance

Duty cycle corrector

Design-for-test technique for a delay locked loop

Quantifying a difference between nodal voltages

Deskewing global clock skew using localized DLLs

Method for optimizing loop bandwidth in delay locked loops

Programmable bias-generator for self-biasing a delay locked loop

Method for reducing supply noise near an on-die thermal sensor

Method and apparatus to store delay locked loop biasing parameters

Jitter estimation for a phase locked loop

Method for decoupling capacitor optimization for a temperature sensor design

Optimization of loop bandwidth for a phase locked loop

Circuit for post-silicon control of delay locked loop charge pump current

Calibration technique for delay locked loop leakage current

Delay locked loop design with switch for loop filter capacitance leakage current control

Programmable current source adjustment of leakage current for delay locked loop

Current crowding reduction technique for flip chip package technology

Updating high speed parallel I/O interfaces based on counters

Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor

Method and apparatus for calibrating a delay locked loop charge pump current

Post-silicon phase offset control of phase locked loop input receiver

Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump

Delay locked loop design with diode for loop filter capacitance leakage current control

Method and system for estimating jitter in a delay locked loop

Post-silicon control of phase locked loop charge pump current

Measuring skew using on-chip sampling

Programmable leakage current offset for delay locked loop

Method for reducing peak to peak jitter in a dual-loop delay locked loop

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop

Method for simulating power supply noise in an on-chip temperature sensor

Reducing voltage variation in a phase locked loop

Verifying on-chip decoupling capacitance

Apparatus for reducing the supply noise near large clock drivers

Non-integer division of frequency

Post-silicon bias-generator control for a differential phase locked loop

Reducing PECL voltage variation

90 degree bump placement layout for an integrated circuit power grid

60 degree bump placement layout for an integrated circuit power grid

XILINX INC

Method and apparatus for a programmably terminated receiver

Method and apparatus for a mesochronous transmission system

Method and apparatus for receive channel data alignment with minimized latency variation

NETLOGIC MICROSYSTEMS INC

Methods and apparatus for generating multiple clocks using feedback interpolation

Methods and apparatus for frequency synthesis with feedback interpolation

AETAS TECHNOLOGY CORP

Electrophotographic color printing arrangement with inclined photoreceptor path

Embedded doctor blade arrangement

NET LOGIC MICROSYSTEMS INC

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

AMMOCORE TECHNOLOGY INC

Integrated circuit block model representation hierarchical handling of timing exceptions

SIDIROPOULOS STEFANOS

Methods and apparatus for frequency synthesis with feedback interpolation

AETAS TECHNOLOGY INC

Belt tension mechanism of an image forming device