Inventor
GREENBERG DAVID R
US22 patents
⚠️ This page may combine multiple inventors who share the name “GREENBERG DAVID R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS6787427B2Sep 7, 2004
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
IBM17 citations92
US6656809B2Dec 2, 2003
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
IBM40 citations92
US6426265B1Jul 30, 2002
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM25 citations92
US7615457B2Nov 10, 2009
Method of fabricating self-aligned bipolar transistor having tapered collector
IBM9 citations84
US7425754B2Sep 16, 2008
Structure and method of self-aligned bipolar transistor having tapered collector
IBM13 citations84
US6836029B2Dec 28, 2004
Micro-electromechanical switch having a conductive compressible electrode
IBM18 citations84
US7767546B1Aug 3, 2010
Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
IBM12 citations83
US7075126B2Jul 11, 2006
Transistor structure with minimized parasitics and method of fabricating the same
IBM9 citations73
US6531720B2Mar 11, 2003
Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors
IBM9 citations73
US6429500B1Aug 6, 2002
Semiconductor pin diode for high frequency applications
IBM11 citations73
US6815802B2Nov 9, 2004
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM5 citations71
US7713829B2May 11, 2010
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM1 citations62
US7642569B2Jan 5, 2010
Transistor structure with minimized parasitics and method of fabricating the same
IBM1 citations62
US7491617B2Feb 17, 2009
Transistor structure with minimized parasitics and method of fabricating the same
IBM2 citations62
US7253070B2Aug 7, 2007
Transistor structure with minimized parasitics and method of fabricating the same
IBM3 citations62
US7355221B2Apr 8, 2008
Field effect transistor having an asymmetrically stressed channel region
IBM3 citations61
US7173274B2Feb 6, 2007
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM0 citations51
DENNARD ROBERT H
2 patentsUS8227865B2Jul 24, 2012
Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
DENNARD ROBERT H5 citations70
US8877606B2Nov 4, 2014
Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
DENNARD ROBERT H2 citations63