Inventor
IP CHUNG-WAH NORRIS
US27 patents
⚠️ This page may combine multiple inventors who share the name “IP CHUNG-WAH NORRIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
11 patentsUS6915248B1Jul 5, 2005
Method and apparatus for transforming test stimulus
CADENCE DESIGN SYSTEMS INC16 citations84
US10380295B1Aug 13, 2019
Methods, systems, and articles of manufacture for X-behavior verification of an electronic design
CADENCE DESIGN SYSTEMS INC2 citations71
US10162917B1Dec 25, 2018
Method and system for implementing selective transformation for low power verification
CADENCE DESIGN SYSTEMS INC5 citations71
US10094875B1Oct 9, 2018
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design
CADENCE DESIGN SYSTEMS INC2 citations71
US9659142B1May 23, 2017
Methods, systems, and articles of manufacture for trace warping for electronic designs
CADENCE DESIGN SYSTEMS INC4 citations68
US9734278B1Aug 15, 2017
Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs
CADENCE DESIGN SYSTEMS INC6 citations65
US10635768B1Apr 28, 2020
System, method, and computer program product for displaying multiple traces while debugging during a formal verification
CADENCE DESIGN SYSTEMS INC1 citations58
US10409945B1Sep 10, 2019
Methods, systems, and computer program product for connectivity verification of electronic designs
CADENCE DESIGN SYSTEMS INC1 citations57
US10331547B1Jun 25, 2019
System, method, and computer program product for capture and reuse in a debug workspace
CADENCE DESIGN SYSTEMS INC0 citations52
US9928328B1Mar 27, 2018
Method and system for automated debugging of a device under test
CADENCE DESIGN SYSTEMS INC1 citations46
US10783304B1Sep 22, 2020
System, method, and computer program product for displaying debugging during a formal verification
CADENCE DESIGN SYSTEMS INC0 citations43
JASPER DESIGN AUTOMATION INC
7 patentsUS7895552B1Feb 22, 2011
Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
JASPER DESIGN AUTOMATION INC30 citations91
US7065726B1Jun 20, 2006
System and method for guiding and optimizing formal verification for a circuit design
JASPER DESIGN AUTOMATION INC36 citations91
US8984461B1Mar 17, 2015
Visualization constraints for circuit designs
JASPER DESIGN AUTOMATION INC7 citations84
US7647572B1Jan 12, 2010
Managing formal verification complexity of designs with multiple related counters
JASPER DESIGN AUTOMATION INC9 citations83
US7506288B1Mar 17, 2009
Interactive analysis and debugging of a circuit design during functional verification of the circuit design
JASPER DESIGN AUTOMATION INC13 citations81
US8990745B1Mar 24, 2015
Manipulation of traces for debugging behaviors of a circuit design
JASPER DESIGN AUTOMATION INC6 citations79
US9081927B2Jul 14, 2015
Manipulation of traces for debugging a circuit design
JASPER DESIGN AUTOMATION INC5 citations68
KRANEN KATHRYN DREWS
3 patentsJASPER DESIGN AUTOMATION
2 patentsUS7159198B1Jan 2, 2007
System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model
JASPER DESIGN AUTOMATION63 citations96
US7437694B1Oct 14, 2008
System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design
JASPER DESIGN AUTOMATION21 citations91