Inventor
PHILIP JOJI
US29 patents
⚠️ This page may combine multiple inventors who share the name “PHILIP JOJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
Netspeed Systems
13 patentsUS8601423B1Dec 3, 2013
Asymmetric mesh NoC topologies
Netspeed Systems118 citations98
US8819611B2Aug 26, 2014
Asymmetric mesh NoC topologies
Netspeed Systems60 citations97
US9742630B2Aug 22, 2017
Configurable router for a network on chip (NoC)
Netspeed Systems23 citations94
US9590813B1Mar 7, 2017
Supporting multicast in NoC interconnect
Netspeed Systems28 citations94
US9473388B2Oct 18, 2016
Supporting multicast in NOC interconnect
Netspeed Systems30 citations94
US9223711B2Dec 29, 2015
Combining associativity and cuckoo hashing
Netspeed Systems47 citations94
US8885510B2Nov 11, 2014
Heterogeneous channel capacities in an interconnect
Netspeed Systems30 citations92
US8819616B2Aug 26, 2014
Asymmetric mesh NoC topologies
Netspeed Systems23 citations92
US10027433B2Jul 17, 2018
Multiple clock domains in NoC
Netspeed Systems7 citations84
US10355996B2Jul 16, 2019
Heterogeneous channel capacities in an interconnect
Netspeed Systems1 citations62
US9825809B2Nov 21, 2017
Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
Netspeed Systems1 citations52
US9781043B2Oct 3, 2017
Identification of internal dependencies within system components for evaluating potential protocol level deadlocks
Netspeed Systems1 citations52
US9774498B2Sep 26, 2017
Hierarchical asymmetric mesh with virtual routers
Netspeed Systems1 citations52
KUMAR SAILESH
6 patentsUS9253085B2Feb 2, 2016
Hierarchical asymmetric mesh with virtual routers
KUMAR SAILESH22 citations92
US9130856B2Sep 8, 2015
Creating multiple NoC layers for isolation or avoiding NoC traffic congestion
KUMAR SAILESH9 citations83
US9009648B2Apr 14, 2015
Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification
KUMAR SAILESH17 citations83
US9185026B2Nov 10, 2015
Tagging and synchronization for fairness in NOC interconnects
KUMAR SAILESH5 citations72
US9007920B2Apr 14, 2015
QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes
KUMAR SAILESH3 citations62
US9135170B2Sep 15, 2015
Memory mapping and translation for arbitrary number of memory units
KUMAR SAILESH0 citations47
NETSPEED SYSTEMS INC
4 patentsUS10983910B2Apr 20, 2021
Bandwidth weighting mechanism based network-on-chip (NoC) configuration
NETSPEED SYSTEMS INC2 citations72
US11144457B2Oct 12, 2021
Enhanced page locality in network-on-chip (NoC) architectures
NETSPEED SYSTEMS INC0 citations51
US10749811B2Aug 18, 2020
Interface virtualization and fast path for Network on Chip
NETSPEED SYSTEMS INC0 citations51
US10735335B2Aug 4, 2020
Interface virtualization and fast path for network on chip
NETSPEED SYSTEMS INC0 citations51
ERICSSON TELEFON AB L M
2 patentsUS12328598B2Jun 10, 2025
Method and system for estimating indoor radio transmitter count
ERICSSON TELEFON AB L M0 citations55
US12402019B2Aug 26, 2025
Method, electronic device and non-transitory computer-readable storage medium for determining indoor radio transmitter distribution
ERICSSON TELEFON AB L M0 citations53