Inventor

CHIANG MIN-HSIUNG

TW32 patents

⚠️ This page may combine multiple inventors who share the name “CHIANG MIN-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIANG MIN-HSIUNG

TAIWAN SEMICONDUCTOR MFG

Method to form a protected metal fuse

Method of reducing nitride and oxide peeling after planarization using an anneal

Method for integrating copper process and MIM capacitor for embedded DRAM

MIM process for logic-based embedded RAM

Approach to integrate salicide gate for embedded DRAM devices

Aperture width reduction method for forming a patterned photoresist layer

Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure

Method of forming layout design

Dual poly layer and method of manufacture

Methods and systems for forming embedded DRAM for an MIM capacitor

Well-controlled CMP process for DRAM technology

Jog design in integrated circuits

MIM process for logic-based embedded RAM having front end manufacturing operation

Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell

Memory cell structure integrating self aligned contact structure with salicide gate electrode structure

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition

Method of improving refresh time in DRAM products

Method to form capacitance node contacts with improved isolation in a DRAM process

Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor

Method to reduce a capacitor depletion phenomena

Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule

Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices

Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal

Method of forming one-transistor memory cell and structure formed thereby

Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming layout design

Jog design in integrated circuits

Jog design in integrated circuits

Semiconductor structure and manufacturing method thereof

TAIWAN SEMICONDUCTOR MANUFACTO

Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins

(unassigned)

Method for forming high purity silicon oxide field oxide isolation region