Inventor
FRODSHAM TIM
US32 patents
⚠️ This page may combine multiple inventors who share the name “FRODSHAM TIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
28 patentsUS6195395B1Feb 27, 2001
Multi-agent pseudo-differential signaling scheme
INTEL CORP250 citations99
US7313712B2Dec 25, 2007
Link power saving state
INTEL CORP71 citations98
US8046488B2Oct 25, 2011
Dynamically modulating link width
INTEL CORP69 citations96
US5483188AJan 9, 1996
Gil edge rate control circuit
INTEL CORP57 citations96
US7957428B2Jun 7, 2011
Methods and apparatuses to effect a variable-width link
INTEL CORP26 citations92
US7610500B2Oct 27, 2009
Link power saving state
INTEL CORP17 citations92
US7209907B2Apr 24, 2007
Method and apparatus for periodically retraining a serial links interface
INTEL CORP18 citations92
US6704892B1Mar 9, 2004
Automated clock alignment for testing processors in a bypass mode
INTEL CORP26 citations92
US6453422B1Sep 17, 2002
Reference voltage distribution for multiload i/o systems
INTEL CORP24 citations90
US7844767B2Nov 30, 2010
Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link
INTEL CORP10 citations84
US7711878B2May 4, 2010
Method and apparatus for acknowledgement-based handshake mechanism for interactively training links
INTEL CORP12 citations84
US7366964B2Apr 29, 2008
Method, system, and apparatus for loopback entry and exit
INTEL CORP10 citations84
US7219220B2May 15, 2007
Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection
INTEL CORP16 citations84
US7203872B2Apr 10, 2007
Cache based physical layer self test
INTEL CORP14 citations84
US7328359B2Feb 5, 2008
Technique to create link determinism
INTEL CORP9 citations83
US7586951B2Sep 8, 2009
Method, apparatus, and system for idle state definition for power management
INTEL CORP8 citations82
US7568118B2Jul 28, 2009
Deterministic operation of an input/output interface
INTEL CORP8 citations80
US7747888B2Jun 29, 2010
Technique to create link determinism
INTEL CORP6 citations73
US7746795B2Jun 29, 2010
Method, system, and apparatus for loopback parameter exchange
INTEL CORP7 citations73
US7362739B2Apr 22, 2008
Methods and apparatuses for detecting clock failure and establishing an alternate clock lane
INTEL CORP7 citations73
US7681093B2Mar 16, 2010
Redundant acknowledgment in loopback entry
INTEL CORP5 citations71
US7804890B2Sep 28, 2010
Method and system for response determinism by synchronization
INTEL CORP7 citations70
US6320441B1Nov 20, 2001
I/O tranceiver having a pulsed latch receiver circuit
INTEL CORP13 citations70
US5721875AFeb 24, 1998
I/O transceiver having a pulsed latch receiver circuit
INTEL CORP15 citations70
US6594769B2Jul 15, 2003
Reference voltage distribution for multiload I/O systems
INTEL CORP10 citations69
US7965741B2Jun 21, 2011
Method, apparatus, and system for idle state definition for power management
INTEL CORP3 citations61
US9794349B2Oct 17, 2017
Dynamically modulating link width
INTEL CORP0 citations51
US7386773B2Jun 10, 2008
Method and system for testing distributed logic circuitry
INTEL CORP0 citations51