Inventor
CHERUKURI NAVEEN
US37 patents
⚠️ This page may combine multiple inventors who share the name “CHERUKURI NAVEEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS7313712B2Dec 25, 2007
Link power saving state
INTEL CORP71 citations98
US8046488B2Oct 25, 2011
Dynamically modulating link width
INTEL CORP69 citations96
US7957428B2Jun 7, 2011
Methods and apparatuses to effect a variable-width link
INTEL CORP26 citations92
US7610500B2Oct 27, 2009
Link power saving state
INTEL CORP17 citations92
US7493228B2Feb 17, 2009
Method and system for deterministic throttling for thermal management
INTEL CORP17 citations92
US7209907B2Apr 24, 2007
Method and apparatus for periodically retraining a serial links interface
INTEL CORP18 citations92
US7979234B2Jul 12, 2011
Method and system for deterministic throttling for thermal management
INTEL CORP7 citations84
US7844767B2Nov 30, 2010
Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link
INTEL CORP10 citations84
US7711878B2May 4, 2010
Method and apparatus for acknowledgement-based handshake mechanism for interactively training links
INTEL CORP12 citations84
US7366964B2Apr 29, 2008
Method, system, and apparatus for loopback entry and exit
INTEL CORP10 citations84
US7219220B2May 15, 2007
Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection
INTEL CORP16 citations84
US7203872B2Apr 10, 2007
Cache based physical layer self test
INTEL CORP14 citations84
US7328359B2Feb 5, 2008
Technique to create link determinism
INTEL CORP9 citations83
US7586951B2Sep 8, 2009
Method, apparatus, and system for idle state definition for power management
INTEL CORP8 citations82
US7746795B2Jun 29, 2010
Method, system, and apparatus for loopback parameter exchange
INTEL CORP7 citations73
US7747888B2Jun 29, 2010
Technique to create link determinism
INTEL CORP6 citations73
US7362739B2Apr 22, 2008
Methods and apparatuses for detecting clock failure and establishing an alternate clock lane
INTEL CORP7 citations73
US10712809B2Jul 14, 2020
Link power savings with state retention
INTEL CORP1 citations72
US10175744B2Jan 8, 2019
Link power savings with state retention
INTEL CORP2 citations72
US9588575B2Mar 7, 2017
Link power savings with state retention
INTEL CORP2 citations72
US7965741B2Jun 21, 2011
Method, apparatus, and system for idle state definition for power management
INTEL CORP3 citations61
US9794349B2Oct 17, 2017
Dynamically modulating link width
INTEL CORP0 citations51
NVIDIA CORP
7 patentsUS11698869B1Jul 11, 2023
Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines
NVIDIA CORP3 citations69
US12141268B2Nov 12, 2024
Secure execution for multiple processor devices using trusted executing environments
NVIDIA CORP2 citations66
US12517798B2Jan 6, 2026
Techniques for memory error isolation
NVIDIA CORP0 citations57
US12219057B2Feb 4, 2025
Implementing trusted executing environments across multiple processor devices
NVIDIA CORP0 citations56
US11720440B2Aug 8, 2023
Error containment for enabling local checkpoint and recovery
NVIDIA CORP1 citations56
US12001592B2Jun 4, 2024
Protecting against resets by untrusted software during cryptographic operations
NVIDIA CORP0 citations55
US11966480B2Apr 23, 2024
Fairly utilizing multiple contexts sharing cryptographic hardware
NVIDIA CORP0 citations48
CHERUKURI NAVEEN
6 patentsUS9424191B2Aug 23, 2016
Scalable coherence for multi-core processors
CHERUKURI NAVEEN9 citations83
US8990506B2Mar 24, 2015
Replacing cache lines in a cache memory based at least in part on cache coherency state information
CHERUKURI NAVEEN17 citations83
US8831666B2Sep 9, 2014
Link power savings with state retention
CHERUKURI NAVEEN11 citations81
US8683136B2Mar 25, 2014
Apparatus and method for improving data prefetching efficiency using history based prefetching
CHERUKURI NAVEEN2 citations61
US8204067B2Jun 19, 2012
Technique for lane virtualization
CHERUKURI NAVEEN1 citations51
US8914541B2Dec 16, 2014
Dynamically modulating link width
CHERUKURI NAVEEN0 citations49