P

Inventor

SCHOENBORN THEODORE Z

US58 patents
⚠️ This page may combine multiple inventors who share the name “SCHOENBORN THEODORE Z”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

42 patents
US10210925B2Feb 19, 2019

Row hammer refresh command

INTEL CORP75 citations98
US9865326B2Jan 9, 2018

Row hammer refresh command

INTEL CORP83 citations98
US9747971B2Aug 29, 2017

Row hammer refresh command

INTEL CORP84 citations98
US7313712B2Dec 25, 2007

Link power saving state

INTEL CORP71 citations98
US8046488B2Oct 25, 2011

Dynamically modulating link width

INTEL CORP69 citations96
US9076499B2Jul 7, 2015

Refresh rate performance based on in-system weak bit detection

INTEL CORP33 citations94
US7324458B2Jan 29, 2008

Physical layer loopback

INTEL CORP28 citations93
US6825693B2Nov 30, 2004

Remote receiver detection

INTEL CORP26 citations93
US7957428B2Jun 7, 2011

Methods and apparatuses to effect a variable-width link

INTEL CORP26 citations92
US7610500B2Oct 27, 2009

Link power saving state

INTEL CORP17 citations92
US7209907B2Apr 24, 2007

Method and apparatus for periodically retraining a serial links interface

INTEL CORP18 citations92
US7464307B2Dec 9, 2008

High performance serial bus testing methodology

INTEL CORP26 citations90
US7444558B2Oct 28, 2008

Programmable measurement mode for a serial point to point link

INTEL CORP39 citations90
US10446222B2Oct 15, 2019

Memory subsystem I/O performance based on in-system empirical testing

INTEL CORP5 citations84
US7936684B2May 3, 2011

Physical layer loopback

INTEL CORP10 citations84
US7844767B2Nov 30, 2010

Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link

INTEL CORP10 citations84
US7711878B2May 4, 2010

Method and apparatus for acknowledgement-based handshake mechanism for interactively training links

INTEL CORP12 citations84
US7366964B2Apr 29, 2008

Method, system, and apparatus for loopback entry and exit

INTEL CORP10 citations84
US7219220B2May 15, 2007

Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection

INTEL CORP16 citations84
US7206981B2Apr 17, 2007

Compliance testing through test equipment

INTEL CORP11 citations84
US7203872B2Apr 10, 2007

Cache based physical layer self test

INTEL CORP14 citations84
US10347319B2Jul 9, 2019

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

INTEL CORP5 citations83
US9373365B2Jun 21, 2016

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

INTEL CORP4 citations83
US9330734B2May 3, 2016

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

INTEL CORP9 citations83
US9009531B2Apr 14, 2015

Memory subsystem data bus stress testing

INTEL CORP10 citations83
US9003246B2Apr 7, 2015

Functional memory array testing with a transaction-level test engine

INTEL CORP9 citations83
US8996934B2Mar 31, 2015

Transaction-level testing of memory I/O and memory device

INTEL CORP10 citations83
US7328359B2Feb 5, 2008

Technique to create link determinism

INTEL CORP9 citations83
US7586951B2Sep 8, 2009

Method, apparatus, and system for idle state definition for power management

INTEL CORP8 citations82
US7427872B2Sep 23, 2008

Asynchronous coupling and decoupling of chips

INTEL CORP8 citations74
US7155352B2Dec 26, 2006

Using feedback to select transmitting voltage

INTEL CORP8 citations74
US7746795B2Jun 29, 2010

Method, system, and apparatus for loopback parameter exchange

INTEL CORP7 citations73
US7747888B2Jun 29, 2010

Technique to create link determinism

INTEL CORP6 citations73
US7362739B2Apr 22, 2008

Methods and apparatuses for detecting clock failure and establishing an alternate clock lane

INTEL CORP7 citations73
US10712809B2Jul 14, 2020

Link power savings with state retention

INTEL CORP1 citations72
US10175744B2Jan 8, 2019

Link power savings with state retention

INTEL CORP2 citations72
US9588575B2Mar 7, 2017

Link power savings with state retention

INTEL CORP2 citations72
US9922725B2Mar 20, 2018

Integrated circuit defect detection and repair

INTEL CORP2 citations70
US9548137B2Jan 17, 2017

Integrated circuit defect detection and repair

INTEL CORP4 citations70
US7804890B2Sep 28, 2010

Method and system for response determinism by synchronization

INTEL CORP7 citations70
US9722663B2Aug 1, 2017

Interference testing

INTEL CORP3 citations69
US7161388B2Jan 9, 2007

Remote receiver detection

INTEL CORP3 citations63

SCHOENBORN THEODORE Z

3 patents

BAINS KULJIT S

1 patent

GREENFIELD ZVIKA

1 patent

MOZAK CHRISTOPHER P

1 patent

CHERUKURI NAVEEN

1 patent

SPRY BRYAN L

1 patent

Showing the top 50 of 58 patents by PatentIndex Score.