Inventor

THEAN VOON-YEW

US57 patents

⚠️ This page may combine multiple inventors who share the name “THEAN VOON-YEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THEAN VOON-YEW

FREESCALE SEMICONDUCTOR INC

Semiconductor device structure and method therefor

Method of making a dual strained channel semiconductor device

Method for forming a semiconductor device having a strained channel and a heterojunction source/drain

Asymmetric spacers and asymmetric source/drain extension layers

Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

Method of forming a FINFET structure

Transistor fabrication using double etch/refill process

Low RC product transistors in SOI semiconductor process

Template layer formation

Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

Double gate device having a heterojunction source/drain and strained channel

Method of manufacturing SOI template layer

Semiconductor transistor having structural elements of differing materials and method of formation

Method of making a semiconductor device with embedded stressor

Twisted dual-substrate orientation (DSO) substrates

Method for PFET enhancement

Semiconductor transistor having structural elements of differing materials

Semiconductor structure having strained semiconductor and method therefor

Channel orientation to enhance transistor performance

Method for transistor fabrication with optimized performance

Method for making a semiconductor device with strain enhancement

Electronic devices including a semiconductor layer

Electronic devices including a semiconductor layer and a process for forming the same

Semiconductor optical devices and method for forming

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors

Semiconductor layer formation

Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit

CMOS process with optimized PMOS and NMOS transistor devices

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Structure and method for strained transistor directly on insulator

Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit

Semiconductor device structure

Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer

Method for forming a semiconductor structure and structure thereof

Semiconductor optical devices having fin structures

Semiconductor optical devices and method for forming

Graded semiconductor layer

Integrated circuit with different channel materials for P and N channel transistors and method therefor

Method for forming vertical structures in a semiconductor device

Engineering strain in thick strained-SOI substrates

Method of forming a semiconductor device having a metal layer

IMEC VZW

Ferroelectric memory device and fabrication method thereof

FinFET device with dual-strained channels and method for manufacturing thereof

IMEC

Methods using mask structures for substantially defect-free epitaxial growth

FinFET device with dual-strained channels and method for manufacturing thereof

IBM

Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors

WINSTEAD BRIAN A

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

LI WEIPENG

Integrated circuit structure having substantially planar N-P step height and methods of forming

SADAKA MARIAM G

Method to selectively form regions having differing properties and structure