Inventor

WHITE TED R

US43 patents

⚠️ This page may combine multiple inventors who share the name “WHITE TED R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WHITE TED R

FREESCALE SEMICONDUCTOR INC

Semiconductor device structure and method therefor

Method for forming a double-gated semiconductor device

Method of making a dual strained channel semiconductor device

Method for forming a semiconductor device having a strained channel and a heterojunction source/drain

Semiconductor structure with different lattice constant materials and method for forming the same

Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor

Modified hybrid orientation technology

SOI active layer with different surface orientation

Transistor fabrication using double etch/refill process

Dual metal gate electrode semiconductor fabrication process and structure thereof

Low RC product transistors in SOI semiconductor process

Template layer formation

Double gate device having a heterojunction source/drain and strained channel

Method of manufacturing SOI template layer

Twisted dual-substrate orientation (DSO) substrates

Semiconductor structure having strained semiconductor and method therefor

Method for making a semiconductor structure using silicon germanium

Channel orientation to enhance transistor performance

Electronic devices including a semiconductor layer

Electronic devices including a semiconductor layer and a process for forming the same

Semiconductor layer formation

Step height reduction between SOI and EPI for DSO and BOS integration

Split gate non-volatile memory cell with improved endurance and method therefor

Transistor with asymmetry for data storage circuitry

Semiconductor device structure

Trench liner for DSO integration

Semiconductor device with stressors and method therefor

Method of making a multiple crystal orientation semiconductor device

Graded semiconductor layer

Integrated circuit with different channel materials for P and N channel transistors and method therefor

Method for forming vertical structures in a semiconductor device

Method for making a semiconductor structure using silicon germanium

Split gate non-volatile memory cell with improved endurance and method therefor

Method for forming a semiconductor structure having a strained silicon layer

MOTOROLA INC

Process for forming a semiconductor device with an antireflective layer

Process for fabricating a non-silicided region in an integrated circuit

Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide

WHITE TED R

Split-gate non-volatile memory cell having improved overlap tolerance and method therefor

Split-gate non-volatile memory cells having improved overlap tolerance

ADETUTU OLUBUNMI O

Method of forming a shared contact in a semiconductor device

Modified hybrid orientation technology

WINSTEAD BRIAN A

Electronic device including a heterojunction region

SADAKA MARIAM G

Method to selectively form regions having differing properties and structure