P

Inventor

EISEN LEE EVAN

US32 patents
⚠️ This page may combine multiple inventors who share the name “EISEN LEE EVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

23 patents
US7194645B2Mar 20, 2007

Method and apparatus for autonomic policy-based thermal management in a data processing system

IBM63 citations97
US9690585B2Jun 27, 2017

Parallel slice processor with dynamic instruction stream mapping

IBM22 citations94
US9690586B2Jun 27, 2017

Processing of multiple instruction streams in a parallel slice processor

IBM26 citations94
US9672043B2Jun 6, 2017

Processing of multiple instruction streams in a parallel slice processor

IBM29 citations94
US9665372B2May 30, 2017

Parallel slice processor with dynamic instruction stream mapping

IBM25 citations94
US6442675B1Aug 27, 2002

Compressed string and multiple generation engine

IBM31 citations92
US6345356B1Feb 5, 2002

Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs

IBM21 citations92
US6286094B1Sep 4, 2001

Method and system for optimizing the fetching of dispatch groups in a superscalar processor

IBM23 citations92
US5790445AAug 4, 1998

Method and system for performing a high speed floating point add operation

IBM29 citations91
US9977678B2May 22, 2018

Reconfigurable parallel execution and load-store slice processor

IBM7 citations84
US9971602B2May 15, 2018

Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices

IBM6 citations84
US6848044B2Jan 25, 2005

Circuits and methods for recovering link stack data upon branch instruction mis-speculation

IBM13 citations84
US6321380B1Nov 20, 2001

Method and apparatus for modifying instruction operations in a processor

IBM18 citations84
US7890738B2Feb 15, 2011

Method and logical apparatus for managing processing system resource use for speculative execution

IBM8 citations82
US10983800B2Apr 20, 2021

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

IBM2 citations73
US10157064B2Dec 18, 2018

Processing of multiple instruction streams in a parallel slice processor

IBM2 citations73
US10083039B2Sep 25, 2018

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

IBM3 citations73
US7254693B2Aug 7, 2007

Selectively prohibiting speculative execution of conditional branch type based on instruction bit

IBM8 citations73
US6385719B1May 7, 2002

Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor

IBM12 citations73
US6098168AAug 1, 2000

System for completing instruction out-of-order which performs target address comparisons prior to dispatch

IBM10 citations73
US6336182B1Jan 1, 2002

System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch

IBM11 citations72
US6430678B1Aug 6, 2002

Scoreboard mechanism for serialized string operations utilizing the XER

IBM3 citations62
US7904697B2Mar 8, 2011

Load register instruction short circuiting method

IBM2 citations61

ADVANCED RISC MACH LTD

9 patents