Inventor

ORION LUC

FR28 patents

⚠️ This page may combine multiple inventors who share the name “ORION LUC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ORION LUC

ADVANCED RISC MACH LTD

Switching between secure and non-secure processing modes

Vectored interrupt control within a system having a secure domain and a non-secure domain

Task following between multiple operating systems

Monitoring control for monitoring at least two domains of multi-domain processors

Exception types within a secure processing system

Exception handling control in a secure processing system

Security mode switching via an exception vector

Function control for a processor

Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain

Delivering data processing requests to a suspended operating system

Error code management in systems permitting partial writes

Exception types within a secure processing system

Handling interrupts in data processing of data in which only a portion of a function has been processed

Handling of hard errors in a cache of a data processing apparatus

Allocation filter for prediction storage structure

Branch prediction circuitry comprising a return address prediction structure and a branch target buffer structure

Apparatus and method for performing branch prediction using loop minimum iteration prediction

Performing at least two branch predictions for non-contiguous instruction blocks at the same time using a prediction mapping

Predicting detected branches as taken when cumulative weight values in a weight table selected by history register bits exceed a threshold value

Apparatus and method for providing decoded instructions from a decoded instruction cache

Apparatus and method for making predictions for branch instructions

Handling multiple interrupts in a data processing system utilising multiple operating systems

Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming

Circuitry and method

Apparatus and method for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period

Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction

ORION LUC

Diagnostic data capture control for multi-domain processors

Method and apparatus for processing data related to handling interrupts in data processing