Inventor
GUPTA SANDEEP KUMAR
US22 patents
⚠️ This page may combine multiple inventors who share the name “GUPTA SANDEEP KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TERANETICS INC
6 patentsUS7015842B1Mar 21, 2006
High-speed sampling architectures
TERANETICS INC45 citations95
US7075471B1Jul 11, 2006
Double-sampled, time-interleaved analog to digital converter
TERANETICS INC39 citations92
US7132965B2Nov 7, 2006
High-speed sampling architectures
TERANETICS INC5 citations65
US7720015B2May 18, 2010
Receiver ADC clock delay base on echo signals
TERANETICS INC5 citations62
US7466746B2Dec 16, 2008
Single amplifier presale processing circuitry
TERANETICS INC2 citations62
US7333448B2Feb 19, 2008
Full duplex transceiver
TERANETICS INC0 citations52
GUPTA SANDEEP KUMAR
5 patentsUS8138839B2Mar 20, 2012
Wideband CMOS gain stage
GUPTA SANDEEP KUMAR4 citations61
US12021526B2Jun 25, 2024
Mixed signal device with different pluralities of digital cells
GUPTA SANDEEP KUMAR1 citations60
US12046601B2Jul 23, 2024
Apparatuses, methods, and systems for an array of devices
GUPTA SANDEEP KUMAR0 citations50
US12021029B2Jun 25, 2024
Systems, methods, and apparatuses for an array of devices
GUPTA SANDEEP KUMAR0 citations50
US11953963B2Apr 9, 2024
Apparatuses and methods for an array of devices
GUPTA SANDEEP KUMAR0 citations50
BROADCOM CORP
3 patentsCIENA CORP
3 patentsUS11528078B1Dec 13, 2022
Reordering a list of restoration paths based on retuning penalties
CIENA CORP0 citations43
US11967984B2Apr 23, 2024
Control plane triggered (CPT) optical protection switching (OPS)
CIENA CORP0 citations42
US11509978B1Nov 22, 2022
Reordering low-priority explicit backup routes to follow implicit backup routes
CIENA CORP0 citations40