P

Inventor

RODGERS SCOTT DION

US43 patents
⚠️ This page may combine multiple inventors who share the name “RODGERS SCOTT DION”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

27 patents
US7949794B2May 24, 2011

PCI express enhancements and extensions

INTEL CORP41 citations95
US5889982AMar 30, 1999

Method and apparatus for generating event handler vectors based on both operating mode and event type

INTEL CORP129 citations95
US7930566B2Apr 19, 2011

PCI express enhancements and extensions

INTEL CORP13 citations92
US7899943B2Mar 1, 2011

PCI express enhancements and extensions

INTEL CORP16 citations92
US5948097ASep 7, 1999

Method and apparatus for changing privilege levels in a computer system without use of a call gate

INTEL CORP44 citations90
US9535838B2Jan 3, 2017

Atomic operations in PCI express

INTEL CORP2 citations84
US9098415B2Aug 4, 2015

PCI express transaction descriptor

INTEL CORP4 citations84
US9032103B2May 12, 2015

Transaction re-ordering

INTEL CORP5 citations84
US9026682B2May 5, 2015

Prefectching in PCI express

INTEL CORP5 citations84
US7849465B2Dec 7, 2010

Programmable event driven yield mechanism which may activate service threads

INTEL CORP18 citations83
US7743233B2Jun 22, 2010

Sequencer address management

INTEL CORP15 citations83
US9990206B2Jun 5, 2018

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

INTEL CORP8 citations82
US10747682B2Aug 18, 2020

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US10180911B2Jan 15, 2019

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9678890B2Jun 13, 2017

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9442855B2Sep 13, 2016

Transaction layer packet formatting

INTEL CORP1 citations63
US9372807B2Jun 21, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP1 citations63
US9372806B2Jun 21, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9330021B2May 3, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9298640B2Mar 29, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9298641B2Mar 29, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9262338B1Feb 16, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9251094B2Feb 2, 2016

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US9141555B2Sep 22, 2015

Synchronizing a translation lookaside buffer with an extended paging table

INTEL CORP0 citations63
US11615031B2Mar 28, 2023

Memory management apparatus and method for managing different page tables for different privilege levels

INTEL CORP0 citations62
US11144472B2Oct 12, 2021

Memory management apparatus and method for managing different page tables for different privilege levels

INTEL CORP0 citations62
US10452403B2Oct 22, 2019

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

INTEL CORP0 citations51

AJANOVIC JASMIN

9 patents

WANG HONG

2 patents

ZOU XIANG

1 patent

PATEL BAIJU V

1 patent

BENNETT STEVEN M

1 patent

ROZAS CARLOS V

1 patent

CHINYA GAUTHAM

1 patent