Inventor

D ABREU MANUEL ANTONIO

US70 patents

⚠️ This page may combine multiple inventors who share the name “D ABREU MANUEL ANTONIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

D ABREU MANUEL ANTONIO

SANDISK TECHNOLOGIES INC

Memory module

Partial block erase for a three dimensional (3D) memory

Parity scheme for a data storage device

Structure variation detection for a memory having a three-dimensional memory configuration

Systems and methods to initiate updating of reference voltages

Data storage device and method for storing multiple codewords and redundancy information at a word line

Multiport memory

Three dimensional memory device having stacked conductive channels

Tracking cell erase counts of non-volatile memory

On-chip copying of data between NAND flash memory and ReRAM of a memory die

Counter for write operations at a data storage device

Selective sense amplifier enablement

Data recovery using additional error correction coding data

System and method of data encoding

Systems and methods to update reference voltages in response to data retention in non-volatile memory

Smart bridge for memory core

Smart bridge for memory core

Smart bridge for memory core

Memory device with resistive random access memory (ReRAM)

Data storage device decoder and method of operation

Three dimensional (3D) memory including error detection circuitry

Parity scheme for a data storage device

Partial block erase for a three dimensional (3D) memory

Memory access techniques for a memory having a three-dimensional memory configuration

Data storage device with in-memory parity circuitry

Tracking read accesses to regions of non-volatile memory

Systems and methods to update reference voltages of non-volatile memory

Apparatus and method of storing data at a multi-bit storage element

D ABREU MANUEL ANTONIO

Method and device for selectively refreshing a region of a memory of a data storage device

System and method of adjusting a programming step size for a block of a memory

System and method responsive to a rate of change of a performance parameter of a memory

Data recovery using additional error correction coding data

Hybrid error correction coding to address uncorrectable errors

System and method of data encoding

System and method of determining a programming step size for a word line of a memory

System and method of tracking error data within a storage device

System and method of interleaving data according to an adjustable parameter

System and method to decode data subject to a disturb condition

Wear leveling of multiple memory devices

Smart bridge for memory core

Data storage device and method to correct bit values using multiple read voltages

System and method to correct data errors using a stored count of bit values

SMART IOPS INC

Devices, systems, and methods of logical-to-physical address mapping

Devices and systems having a protocol-independent interface supporting a plurality of data protocols, and methods related thereto

Devices, systems, and methods for increasing endurance on a storage system having a plurality of components using adaptive code-rates

SANDISK TECHNOLOGIES LLC

Error correcting code adjustment for a data storage device

Apparatus and method of offloading processing from a data storage device to a host device

D'ABREU MANUEL ANTONIO

Smart bridge for memory core

PANCHOLI DEEPAK

Statistical distribution based variable-bit error correction coding

VENKITACHALAM ANAND

Systems and methods of updating read voltages