Inventor
RAO JAYANTH N
US16 patents
⚠️ This page may combine multiple inventors who share the name “RAO JAYANTH N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
13 patentsUS9514559B2Dec 6, 2016
Memory sharing via a unified memory architecture
INTEL CORP7 citations83
US10929304B2Feb 23, 2021
Memory sharing via a unified memory architecture
INTEL CORP2 citations72
US10521874B2Dec 31, 2019
Method and apparatus for a highly efficient graphics processing unit (GPU) execution model
INTEL CORP3 citations68
US10068306B2Sep 4, 2018
Facilitating dynamic pipelining of workload executions on graphics processing units on computing devices
INTEL CORP5 citations67
US11531623B2Dec 20, 2022
Memory sharing via a unified memory architecture
INTEL CORP0 citations62
US10937118B2Mar 2, 2021
Scheduling and dispatch of GPGPU workloads
INTEL CORP0 citations59
US9606919B2Mar 28, 2017
Method and apparatus to facilitate shared pointers in a heterogeneous platform
INTEL CORP0 citations52
US8862831B2Oct 14, 2014
Method and apparatus to facilitate shared pointers in a heterogeneous platform
INTEL CORP0 citations52
US10198361B2Feb 5, 2019
Memory sharing via a unified memory architecture
INTEL CORP0 citations51
US9892480B2Feb 13, 2018
Aborting graphics processor workload execution
INTEL CORP0 citations51
US9779472B2Oct 3, 2017
Shared virtual memory
INTEL CORP1 citations50
US10235732B2Mar 19, 2019
Scheduling and dispatch of GPGPU workloads
INTEL CORP0 citations49
US9449363B2Sep 20, 2016
Sampling, fault management, and/or context switching via a compute pipeline
INTEL CORP0 citations27