Inventor

SHUE SHAU-LIN

TW379 patents

⚠️ This page may combine multiple inventors who share the name “SHUE SHAU-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHUE SHAU-LIN

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology

Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process

Multi-step plasma process for forming TiSiN barrier

Lightly nitridation surface for preparing thin-gate oxides

In-situ cleaning process for Cu metallization

Self aligned dual damascene process and structure with low parasitic capacitance

Method for improvement of gap filling capability of electrochemical deposition of copper

Method to solve via poisoning for porous low-k dielectric

Method of barrier-less integration with copper alloy

Method to improve copper via electromigration (EM) resistance

Method of copper barrier layer formation

Lightly nitridation surface for preparing thin-gate oxides

Self-passivation procedure for a copper damascene structure

Self-passivation of copper damascene

Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure

Temporary carrier bonding and detaching processes

Multi-step electrochemical copper deposition process with improved filling capability

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Cleaning processes in the formation of integrated circuit interconnect structures

Semiconductor structure including silicide regions and method of making same

Barrier structure for semiconductor devices

Method of forming silicided gate structure

Adhesion of copper and etch stop layer for copper alloy

Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing

Eliminate broken line damage of copper after CMP

Method for forming a self-passivated copper interconnect structure

Sidewall coverage for copper damascene filling

Method for selectively depositing diffusion barriers

Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure

Method for forming incompletely landed via with attenuated contact resistance

Methods for edge alignment mark protection during damascene electrochemical plating of copper

Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process

Method of forming barrier and seed layers for electrochemical deposition of copper

Via RC improvement for copper damascene and beyond technology

Process for forming an integrated contact or via

Stress management of barrier metal for resolving CU line corrosion

Passivation method of post copper dry etching

Effective diffusion barrier process and device manufactured thereby

AlCu electromigration (EM) resistance

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of spacer patterning to form a target integrated circuit pattern

Method of forming metal interconnection

Method of forming metal interconnection

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Lithography using high selectivity spacers for pitch reduction

Semiconductor device and manufacturing method thereof

Method of fabricating semiconductor device with reduced trench distortions

CHEN MING-FA

Wafer backside interconnect structure connected to TSVs

CHANG HUNG-PIN

Multi-layer interconnect structure for stacked dies