Inventor

KIRIHATA TOSHIAKI

US145 patents

⚠️ This page may combine multiple inventors who share the name “KIRIHATA TOSHIAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIRIHATA TOSHIAKI

IBM

Hierarchical column select line architecture for multi-bank DRAMs

Defect management engine for semiconductor memories and memory systems

Conductor-insulator-conductor structure

Intra-unit block addressing system for memory

Built in self test with memory

Latched row decoder for a random access memory

Bit-line precharge current limiter for CMOS dynamic memories

Method of self programmed built in self test

Address wrap function for addressable memory devices

Concurrent refresh mode with distributed row address counters in an embedded DRAM

Method of reducing sub-threshold leakage in circuits during standby mode

Self-adjusting burn-in test

Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells

Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array

SDRAM with a maskable input

Sub-block redundancy replacement for a giga-bit scale DRAM

Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device

Method of structuring a multi-bank DRAM into a hierarchical column select line architecture

Prioritizing the repair of faults in a semiconductor memory device

Variable size redundancy replacement architecture to make a memory fault-tolerant

Method of making a memory fault-tolerant using a variable size redundancy replacement configuration

Method of testing a random access memory

DRAM signal margin test method

Random access memory having a flexible array redundancy scheme

Hierarchical in-memory sort engine

Self-authenticating of chip based on intrinsic features

Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology

Random access electrically programmable e-fuse ROM

Apparatus and method for improving sensing margin of electrically programmable fuses

Single cycle refresh of multi-port dynamic random access memory (DRAM)

Flexible row redundancy system

High performance gain cell architecture

Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology

Gain cell structure with deep trench capacitor

CBR refresh control for the redundancy array

Method for addressing electrical fuses

Self programmed built in self test

Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains

High performance on-chip voltage regulator designs

Row redundancy block architecture

Variable bitline precharge voltage sensing technique for DRAM structures

Sensing circuit for semiconductor memory with limited bitline voltage swing

Destructive read architecture for dynamic random access memories

Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture

SIEMENS AG

Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines

High density semiconductor memory having diagonal bit lines and dual word lines

Semiconductor memory having hierarchical bit line and/or word line architecture

Semiconductor memory having space-efficient layout

Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements

INFINEON TECHNOLOGIES AG

Semiconductor memory with programmable bitline multiplexers