Inventor
ORZOL NICHOLAS R
US17 patents
Patents
17 patentsUS11392386B2Jul 19, 2022
Program counter (PC)-relative load and store addressing for fused instructions
IBM2 citations72
US10037207B2Jul 31, 2018
Power management of branch predictors in a computer processor
IBM2 citations71
US9996351B2Jun 12, 2018
Power management of branch predictors in a computer processor
IBM2 citations71
US10037259B2Jul 31, 2018
Adaptive debug tracing for microprocessors
IBM3 citations68
US11886883B2Jan 30, 2024
Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction
IBM0 citations62
US10740104B2Aug 11, 2020
Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch
IBM1 citations61
US11663013B2May 30, 2023
Dependency skipping execution
IBM0 citations51
US10528347B2Jan 7, 2020
Executing system call vectored instructions in a multi-slice processor
IBM0 citations51
US10048963B2Aug 14, 2018
Executing system call vectored instructions in a multi-slice processor
IBM0 citations51
US11593108B2Feb 28, 2023
Sharing instruction cache footprint between multiple threads
IBM0 citations50
US11593109B2Feb 28, 2023
Sharing instruction cache lines between multiple threads
IBM0 citations50
US11416257B2Aug 16, 2022
Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through
IBM0 citations50
US10552159B2Feb 4, 2020
Power management of branch predictors in a computer processor
IBM0 citations50
US11106466B2Aug 31, 2021
Decoupling of conditional branches
IBM0 citations48
US10678551B2Jun 9, 2020
Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction
IBM0 citations41
US10275256B2Apr 30, 2019
Branch prediction in a computer processor
IBM0 citations37
US10127121B2Nov 13, 2018
Operation of a multi-slice processor implementing adaptive failure state capture
IBM0 citations37