Inventor
PATEL PRADIP
US27 patents
⚠️ This page may combine multiple inventors who share the name “PATEL PRADIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS5659551AAug 19, 1997
Programmable computer system element with built-in self test method and apparatus for repair during power-on
IBM117 citations97
US7257745B2Aug 14, 2007
Array self repair using built-in self test techniques
IBM22 citations92
US5805789ASep 8, 1998
Programmable computer system element with built-in self test method and apparatus for repair during power-on
IBM49 citations92
US5633877AMay 27, 1997
Programmable built-in self test method and controller for arrays
IBM52 citations89
US7478297B2Jan 13, 2009
Merged MISR and output register without performance impact for circuits under test
IBM8 citations84
US8055960B2Nov 8, 2011
Self test apparatus for identifying partially defective memory
IBM10 citations81
US7305602B2Dec 4, 2007
Merged MISR and output register without performance impact for circuits under test
IBM8 citations74
US9697910B1Jul 4, 2017
Multi-match error detection in content addressable memory testing
IBM3 citations73
US9627012B1Apr 18, 2017
Shift register with opposite shift data and shift clock directions
IBM5 citations72
US10593420B2Mar 17, 2020
Testing content addressable memory and random access memory
IBM2 citations71
US10170199B2Jan 1, 2019
Testing content addressable memory and random access memory
IBM2 citations71
US10079070B2Sep 18, 2018
Testing content addressable memory and random access memory
IBM2 citations71
US10971242B2Apr 6, 2021
Sequential error capture during memory test
IBM2 citations70
US10998075B2May 4, 2021
Built-in self-test for bit-write enabled memory arrays
IBM2 citations68
US10890623B1Jan 12, 2021
Power saving scannable latch output driver
IBM2 citations66
US6629280B1Sep 30, 2003
Method and apparatus for delaying ABIST start
IBM3 citations62
US7529997B2May 5, 2009
Method for self-correcting cache using line delete, data logging, and fuse repair correction
IBM3 citations61
US7366953B2Apr 29, 2008
Self test method and apparatus for identifying partially defective memory
IBM5 citations59
US7536613B2May 19, 2009
BIST address generation architecture for multi-port memories
IBM0 citations51
US9983261B2May 29, 2018
Partition-able storage of test results using inactive storage elements
IBM0 citations41
US7275194B2Sep 25, 2007
Clock duty cycle based access timer combined with standard stage clocked output register
IBM0 citations41