Inventor

SAUTTER ROLF

DE46 patents

⚠️ This page may combine multiple inventors who share the name “SAUTTER ROLF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAUTTER ROLF

IBM

Single-ended read and differential write scheme

Read/write alignment scheme for port reduction of multi-port SRAM cells

Structure for reducing pre-charge voltage for static random-access memory arrays

Clock driver and boundary latch for a multi-port SRAM

Hierarchical negative bitline boost write assist for SRAM memory devices

Microelectronic device with a memory element utilizing stacked vertical devices

Buried conductive layer supplying digital circuits

Structure for reducing pre-charge voltage for static random-access memory arrays

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Power saving by disabling cyclic bitline precharge

Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates

Content addressable memory

Method and system for fast access to a translation lookaside buffer

Layout of a memory cell of an integrated circuit

Content addressable memory cell and array

Progamable control clock circuit for arrays

Dynamic adjustment of signal delay with memory array voltage

Integrated circuit including logic circuitry

Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments

Midcycle latch for power saving and switching reduction

Enhanced programmable pulsewidth modulating circuit for array clock generation

Circuit combining level shift function with gated reset

Advanced array local clock buffer base block circuit

True complement dynamic circuit and method for combining binary data

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

Multiple port memory apparatus

Integrated circuit with vertical structures on nodes of a grid

Microelectronic device utilizing stacked vertical devices

Structure for reducing pre-charge voltage for static random-access memory arrays

Structure for reducing pre-charge voltage for static random-access memory arrays

Structure for reducing pre-charge voltage for static random-access memory arrays

Adder structure with midcycle latch for power reduction

Current-mode sense amplifier and reference current circuitry

Current-mode sense amplifier and reference current circuitry

Content addressable memory device

Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages

Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block

Array delete mechanisms for shipping a microprocessor with defective arrays

Current-mode sense amplifier

DENGLER OSAMA

Enhanced power savings for memory arrays

CHAN YUEN H

Low power programmable clock delay generator with integrated decode function

BUETTNER STEFAN

Reduced power consumption memory circuitry

HALLER WILHELM

Adder structure with midcycle latch for power reduction