Inventor
CHAWLA HITESH
IN12 patents
⚠️ This page may combine multiple inventors who share the name “CHAWLA HITESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILVEREDGE TECH PVT LTD
7 patentsUS10733453B2Aug 4, 2020
Method and system for supervised detection of televised video ads in live stream media content
SILVEREDGE TECH PVT LTD0 citations35
US10719715B2Jul 21, 2020
Method and system for adaptively switching detection strategies for watermarked and non-watermarked real-time televised advertisements
SILVEREDGE TECH PVT LTD0 citations35
US10719714B2Jul 21, 2020
Method and system for adaptively reducing detection time in real-time supervised detection of televised advertisements
SILVEREDGE TECH PVT LTD0 citations35
US10713496B2Jul 14, 2020
Method and system for hardware, channel, language and ad length agnostic detection of televised advertisements
SILVEREDGE TECH PVT LTD0 citations35
US10149022B2Dec 4, 2018
Method and system of auto-tagging brands of television advertisements
SILVEREDGE TECH PVT LTD0 citations35
US10117000B2Oct 30, 2018
Method and system for hardware agnostic detection of television advertisements
SILVEREDGE TECH PVT LTD0 citations35
US9894412B2Feb 13, 2018
Method and system for detection of television advertisements using broadcasting channel characteristics
SILVEREDGE TECH PVT LTD0 citations35
ST MICROELECTRONICS INT NV
5 patentsUS9865333B2Jan 9, 2018
Temperature compensated read assist circuit for a static random access memory (SRAM)
ST MICROELECTRONICS INT NV7 citations82
US12584961B2Mar 24, 2026
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
ST MICROELECTRONICS INT NV0 citations50
US12437825B2Oct 7, 2025
At-speed transition fault testing for a multi-port and multi-clock memory
ST MICROELECTRONICS INT NV0 citations50
US12353341B2Jul 8, 2025
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
ST MICROELECTRONICS INT NV0 citations50
US12170120B2Dec 17, 2024
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
ST MICROELECTRONICS INT NV0 citations50