Inventor
KOTHAMASU SIVA SRINIVAS
US11 patents
Patents
11 patentsUS10387690B2Aug 20, 2019
Integrated power supply scheme for powering memory card host interface
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US12141030B2Nov 12, 2024
Accessing error statistics from DRAM memories having integrated error correction
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US11714713B2Aug 1, 2023
Accessing error statistics from dram memories having integrated error correction
TEXAS INSTRUMENTS INC1 citations70
US11403171B2Aug 2, 2022
Accessing error statistics from DRAM memories having integrated error correction
TEXAS INSTRUMENTS INC1 citations70
US10572344B2Feb 25, 2020
Accessing error statistics from DRAM memories having integrated error correction
TEXAS INSTRUMENTS INC1 citations70
US9627035B2Apr 18, 2017
Fail-safe I/O to achieve ultra low system power
TEXAS INSTRUMENTS INC3 citations69
US9471140B2Oct 18, 2016
Valid context status retention in processor power mode management
TEXAS INSTRUMENTS INC4 citations65
US12271289B2Apr 8, 2025
System on a chip with an integrated configurable safety master microcontroller unit
TEXAS INSTRUMENTS INC0 citations56
US11899563B2Feb 13, 2024
System on a chip with an integrated configurable safety master microcontroller unit
TEXAS INSTRUMENTS INC0 citations56
US10262722B2Apr 16, 2019
Fail-safe input/output (IO) circuit
TEXAS INSTRUMENTS INC0 citations48
US12493340B2Dec 9, 2025
Power-on-reset signal isolation during lower power mode
TEXAS INSTRUMENTS INC0 citations44