Inventor

WERKHEISER MARK DAVID

US31 patents

⚠️ This page may combine multiple inventors who share the name “WERKHEISER MARK DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WERKHEISER MARK DAVID

ADVANCED RISC MACH LTD

Apparatus and method for managing snoop operations

System, method and apparatus for enabling partial data transfers with indicators

Inter-chip communication in a multi-chip system

Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit

Configurable cache coherency controller

Snoop filter for cache coherency in a data processing system

Read-with overridable-invalidate transaction

Snoop filter for cache coherency in a data processing system

Progressive fine to coarse grain snoop filter

Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit

Apparatus and method for routing access requests in an interconnect

Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation

Clock circuitry for functionally safe systems

System, method and apparatus for ordering logic

Interconnect resource allocation

System, method and apparatus for accessing shared memory

CCIX port management for PCI express traffic

Writing zero data

Apparatus and method for handling ordered transactions

Apparatus and method for handling memory access requests

Clock circuitry with fault detection

Write operation status

Data processing network with super home node

Transaction requests according to a request ordering protocol

Distributed virtual memory management for data processing network

Methods and apparatus for communicating between node devices

Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths

Segregated power state control in a distributed cache system

JALAL JAMSHED

Snoop filter and non-inclusive shared cache memory

Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode