Inventor

BOEMMELS JUERGEN

BE30 patents

⚠️ This page may combine multiple inventors who share the name “BOEMMELS JUERGEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOEMMELS JUERGEN

IMEC VZW

Semiconductor device having stacked transistor pairs and method of forming same

Method for interrupting a line in an interconnect

Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices

Self-aligned interconnects

Self-aligned layer patterning

Method of forming vertical channel devices

3D integrated count

3D integrated circuit

Standard cell device and method of forming an interconnect structure for a standard cell device

Semiconductor device having vertical transistors and method of forming same

Method for forming an interconnection structure

Self-aligned contacts for nanosheet field effect transistor devices

Method for forming transistor structures

Method for forming a stacked FET device

Method of patterning target layer

Self-aligned gate contact

Three-dimensional semiconductor device and method of manufacturing same

Method of forming vertical channel devices

Vertical channel devices and method of fabricating same

Method for forming a multi-level interconnect structure

Semiconductor device and method

ADVANCED MICRO DEVICES INC

Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

Semiconductor device including field effect transistors laterally enclosed by interlayer dielectric material having increased intrinsic stress

Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices

RICHTER RALF

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

GLOBALFOUNDRIES INC

Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices

BOEMMELS JUERGEN

Semiconductor device having a grain orientation layer

SCHUEHRER HOLGER

Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer

FROHBERG KAI

Dual contact metallization including electroless plating in a semiconductor device