P

Inventor

RYCKAERT JULIEN

BE34 patents
⚠️ This page may combine multiple inventors who share the name “RYCKAERT JULIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IMEC VZW

30 patents
US10636739B2Apr 28, 2020

Integrated circuit chip with power delivery network on the backside of the chip

IMEC VZW89 citations98
US11164942B1Nov 2, 2021

Method for forming nanosheet transistor structures

IMEC VZW21 citations92
US11244949B2Feb 8, 2022

Semiconductor device having stacked transistor pairs and method of forming same

IMEC VZW9 citations84
US10607896B2Mar 31, 2020

Method of forming gate of semiconductor device and semiconductor device having same

IMEC VZW9 citations83
US10332588B2Jun 25, 2019

Static random access memory device having interconnected stacks of transistors

IMEC VZW7 citations82
US10403627B2Sep 3, 2019

Memory device for a dynamic random access memory

IMEC VZW12 citations80
US10242907B2Mar 26, 2019

Method for interrupting a line in an interconnect

IMEC VZW5 citations73
US11515399B2Nov 29, 2022

Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices

IMEC VZW3 citations71
US11018235B2May 25, 2021

Vertically stacked semiconductor devices having vertical channel transistors

IMEC VZW2 citations71
US10720363B2Jul 21, 2020

Method of forming vertical transistor device

IMEC VZW6 citations71
US11335597B2May 17, 2022

Method for forming a buried metal line

IMEC VZW1 citations62
US11342261B2May 24, 2022

Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same

IMEC VZW0 citations61
US11211404B2Dec 28, 2021

Memory devices based on ferroelectric field effect transistors

IMEC VZW0 citations61
US11677401B2Jun 13, 2023

3D integrated count

IMEC VZW0 citations60
US11381242B2Jul 5, 2022

3D integrated circuit

IMEC VZW0 citations60
US11201093B2Dec 14, 2021

Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET

IMEC VZW1 citations59
US12484289B2Nov 25, 2025

Method for forming a stacked transistor device

IMEC VZW0 citations52
US12324175B2Jun 3, 2025

FET device and a method for forming a FET device

IMEC VZW0 citations52
US12446246B2Oct 14, 2025

Field-effect transistor device

IMEC VZW0 citations51
US11295977B2Apr 5, 2022

Standard cell device and method of forming an interconnect structure for a standard cell device

IMEC VZW0 citations51
US11462443B2Oct 4, 2022

Self-aligned contacts for nanosheet field effect transistor devices

IMEC VZW0 citations50
US12424276B2Sep 23, 2025

Multiport memory cells including stacked active layers

IMEC VZW0 citations49
US12446247B2Oct 14, 2025

Circuit cell for a standard cell semiconductor device

IMEC VZW0 citations47
US12557378B2Feb 17, 2026

Complementary field-effect transistor device

IMEC VZW0 citations45
US10847415B2Nov 24, 2020

Self-aligned gate contact

IMEC VZW0 citations41
US10748815B2Aug 18, 2020

Three-dimensional semiconductor device and method of manufacturing same

IMEC VZW0 citations41
US10043798B2Aug 7, 2018

Buried interconnect for semiconductor circuits

IMEC VZW0 citations40
US10522552B2Dec 31, 2019

Method of fabricating vertical transistor device

IMEC VZW0 citations39
US10833161B2Nov 10, 2020

Semiconductor device and method

IMEC VZW0 citations37
US10460067B2Oct 29, 2019

Method of patterning target layer

IMEC VZW0 citations36

IMEC

3 patents

BOS LYNN

1 patent