Inventor
SESHAN LAKSHMIPRIYA
US17 patents
Patents
17 patentsUS10686582B1Jun 16, 2020
Clock phase compensation apparatus and method
INTEL CORP17 citations81
US12360934B2Jul 15, 2025
Parameter exchange for a die-to-die interconnect
INTEL CORP2 citations74
US12332826B2Jun 17, 2025
Die-to-die interconnect
INTEL CORP2 citations74
US12481614B2Nov 25, 2025
Standard interfaces for die to die (D2D) interconnect stacks
INTEL CORP1 citations63
US12353305B2Jul 8, 2025
Compliance and debug testing of a die-to-die interconnect
INTEL CORP1 citations63
US12554672B2Feb 17, 2026
Link layer-PHY interface adapter
INTEL CORP0 citations62
US12499019B2Dec 16, 2025
Retimers to extend a die-to-die interconnect
INTEL CORP0 citations62
US12468597B2Nov 11, 2025
Valid signal for latency sensitive die-to-die (D2D) interconnects
INTEL CORP0 citations62
US12362306B2Jul 15, 2025
Clock-gating in die-to-die (D2D) interconnects
INTEL CORP0 citations62
US12316343B2May 27, 2025
PHY-based retry techniques for die-to-die interfaces
INTEL CORP0 citations62
US11971841B2Apr 30, 2024
Link layer-PHY interface adapter
INTEL CORP0 citations62
US12117960B2Oct 15, 2024
Approximate data bus inversion technique for latency sensitive applications
INTEL CORP1 citations61
US12591727B2Mar 31, 2026
Lane repair and lane reversal implementation for die-to-die (D2D) interconnects
INTEL CORP0 citations51
US12405912B2Sep 2, 2025
Link initialization training and bring up for die-to-die interconnect
INTEL CORP0 citations51
US12321305B2Jun 3, 2025
Sideband interface for die-to-die interconnects
INTEL CORP0 citations51
US12298833B2May 13, 2025
Performance level control in a data processing apparatus
INTEL CORP0 citations48
US12159840B2Dec 3, 2024
Scalable and interoperable PHYLESS die-to-die IO solution
INTEL CORP0 citations46