Inventor
PASDAST GERALD
US34 patents
Patents
34 patentsUS6326802B1Dec 4, 2001
On-die adaptive arrangements for continuous process, voltage and temperature compensation
INTEL CORP42 citations91
US11270947B2Mar 8, 2022
Composite interposer structure and method of providing same
INTEL CORP5 citations84
US11094672B2Aug 17, 2021
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
INTEL CORP5 citations84
US11652059B2May 16, 2023
Composite interposer structure and method of providing same
INTEL CORP5 citations82
US10795853B2Oct 6, 2020
Multiple dies hardware processors and methods
INTEL CORP9 citations82
US10686582B1Jun 16, 2020
Clock phase compensation apparatus and method
INTEL CORP17 citations81
US12332826B2Jun 17, 2025
Die-to-die interconnect
INTEL CORP2 citations74
US11586579B2Feb 21, 2023
Multiple dies hardware processors and methods
INTEL CORP2 citations71
US11205630B2Dec 21, 2021
Vias in composite IC chip structures
INTEL CORP3 citations71
US12481614B2Nov 25, 2025
Standard interfaces for die to die (D2D) interconnect stacks
INTEL CORP1 citations63
US12353305B2Jul 8, 2025
Compliance and debug testing of a die-to-die interconnect
INTEL CORP1 citations63
US12505065B2Dec 23, 2025
On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY
INTEL CORP0 citations62
US12499019B2Dec 16, 2025
Retimers to extend a die-to-die interconnect
INTEL CORP0 citations62
US12468597B2Nov 11, 2025
Valid signal for latency sensitive die-to-die (D2D) interconnects
INTEL CORP0 citations62
US12362284B2Jul 15, 2025
Composite interposer structure and method of providing same
INTEL CORP0 citations62
US12362306B2Jul 15, 2025
Clock-gating in die-to-die (D2D) interconnects
INTEL CORP0 citations62
US12014990B2Jun 18, 2024
Composite interposer structure and method of providing same
INTEL CORP0 citations62
US11749649B2Sep 5, 2023
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
INTEL CORP0 citations62
US10998302B2May 4, 2021
Packaged device with a chiplet comprising memory resources
INTEL CORP0 citations62
US12578384B2Mar 17, 2026
Unified test and debug chiplet architecture
INTEL CORP0 citations61
US12315794B2May 27, 2025
Skip level vias in metallization layers for integrated circuit devices
INTEL CORP0 citations61
US12288746B2Apr 29, 2025
Skip level vias in metallization layers for integrated circuit devices
INTEL CORP0 citations61
US11899615B2Feb 13, 2024
Multiple dies hardware processors and methods
INTEL CORP0 citations61
US11694986B2Jul 4, 2023
Vias in composite IC chip structures
INTEL CORP0 citations61
US11294852B2Apr 5, 2022
Multiple dies hardware processors and methods
INTEL CORP0 citations61
US12164319B2Dec 10, 2024
Dual loop voltage regulator
INTEL CORP0 citations60
US12500583B2Dec 16, 2025
Clock interpolation system for eye-centering
INTEL CORP0 citations59
US12306216B2May 20, 2025
Dynamic voltage regulator sensing for chiplet-based designs
INTEL CORP0 citations57
US12591727B2Mar 31, 2026
Lane repair and lane reversal implementation for die-to-die (D2D) interconnects
INTEL CORP0 citations51
US12405912B2Sep 2, 2025
Link initialization training and bring up for die-to-die interconnect
INTEL CORP0 citations51
US12321305B2Jun 3, 2025
Sideband interface for die-to-die interconnects
INTEL CORP0 citations51
US12100662B2Sep 24, 2024
Power-forwarding bridge for inter-chip data signal transfer
INTEL CORP0 citations51
US12159840B2Dec 3, 2024
Scalable and interoperable PHYLESS die-to-die IO solution
INTEL CORP0 citations46
US10854548B2Dec 1, 2020
Inter-die passive interconnects approaching monolithic performance
INTEL CORP0 citations42