Inventor

STRIRAMASSARMA LAKSHMINARAYANAN

US51 patents

⚠️ This page may combine multiple inventors who share the name “STRIRAMASSARMA LAKSHMINARAYANAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STRIRAMASSARMA LAKSHMINARAYANAN

INTEL CORP

Systems and methods for improving cache efficiency and utilization

Sparse optimizations for a matrix accelerator architecture

Disaggregation of SOC architecture

Graphics processor data access and sharing

Systems and methods for cache optimization

Systems and methods for improving cache efficiency and utilization

Multi-tile architecture for graphics operations

Dynamic memory reconfiguration

Efficient data sharing for graphics data processing operations

Disaggregation of system-on-chip (SOC) architecture

Sparse optimizations for a matrix accelerator architecture

Disaggregation of System-On-Chip (SOC) architecture

Multi-tile memory management

Systolic disaggregation within a matrix accelerator architecture

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Multi-tile graphics processor rendering

Data prefetching for graphics data processing

Partial write management in a multi-tiled compute engine

Cache structure and utilization

Systems and methods for cache optimization

Systems and methods for cache optimization

Assistance for hardware prefetch in cache access

Dynamic memory reconfiguration

Cache structure and utilization

Multi-tile memory management

Sector cache for compression

Multi-tile memory management

Efficient data sharing for graphics data processing operations

Enabling product SKUS based on chiplet configurations

Enabling product SKUs based on chiplet configurations

Sector cache for compression

Data distribution fabric in scalable GPUs

Data distribution fabric in scalable GPUs

Graphics processor register file including a low energy portion and a high capacity portion

Sector cache for compression

Sector cache for compression

Sector cache for compression

Efficient data sharing for graphics data processing operations

Sparse optimizations for a matrix accelerator architecture

Enabling product SKUs based on chiplet configurations

Disaggregation of system-on-chip (SOC) architecture

Multi-tile graphics processor rendering

Disaggregation of system-on-chip (SOC) architecture

Data prefetching for graphics data processing

Disaggregation of system-on-chip (SOC) architecture

Data prefetching for graphics data processing

Partial write management in a multi-tiled compute engine

Data distribution fabric in scalable GPUs

Energy efficient memory array with optimized burst read and write data access

KOKER ALTUG

Data distribution fabric in scalable GPUs