Inventor
KILLIAN EARL A
US34 patents
⚠️ This page may combine multiple inventors who share the name “KILLIAN EARL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TENSILICA INC
12 patentsUS7020854B2Mar 28, 2006
Automated processor generation system for designing a configurable processor and method for the same
TENSILICA INC152 citations98
US6477683B1Nov 5, 2002
Automated processor generation system for designing a configurable processor and method for the same
TENSILICA INC437 citations98
US8006204B2Aug 23, 2011
Automated processor generation system for designing a configurable processor and method for the same
TENSILICA INC70 citations97
US7036106B1Apr 25, 2006
Automated processor generation system for designing a configurable processor and method for the same
TENSILICA INC109 citations97
US6760888B2Jul 6, 2004
Automated processor generation system for designing a configurable processor and method for the same
TENSILICA INC148 citations97
US6477697B1Nov 5, 2002
Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
TENSILICA INC88 citations97
US6282633B1Aug 28, 2001
High data density RISC processor
TENSILICA INC104 citations97
US7376812B1May 20, 2008
Vector co-processor for configurable and extensible processor architecture
TENSILICA INC78 citations96
US7219212B1May 15, 2007
Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion
TENSILICA INC121 citations96
US6854046B1Feb 8, 2005
Configurable memory management unit
TENSILICA INC100 citations94
US7346881B2Mar 18, 2008
Method and apparatus for adding advanced instructions in an extensible processor architecture
TENSILICA INC14 citations83
US7437700B2Oct 14, 2008
Automated processor generation system and method for designing a configurable processor
TENSILICA INC7 citations72
MIPS TECH INC
9 patentsUS5933650AAug 3, 1999
Alignment and ordering of vector elements for single instruction multiple data processing
MIPS TECH INC352 citations99
US5864703AJan 26, 1999
Method for providing extended precision in SIMD vector arithmetic operations
MIPS TECH INC204 citations99
US7197625B1Mar 27, 2007
Alignment and ordering of vector elements for single instruction multiple data processing
MIPS TECH INC61 citations98
US6266758B1Jul 24, 2001
Alignment and ordering of vector elements for single instruction multiple data processing
MIPS TECH INC193 citations97
US6092187AJul 18, 2000
Instruction prediction based on filtering
MIPS TECH INC51 citations96
US6425076B1Jul 23, 2002
Instruction prediction based on filtering
MIPS TECH INC25 citations93
US7159100B2Jan 2, 2007
Method for providing extended precision in SIMD vector arithmetic operations
MIPS TECH INC23 citations92
US7546443B2Jun 9, 2009
Providing extended precision in SIMD vector arithmetic operations
MIPS TECH INC8 citations84
US7793077B2Sep 7, 2010
Alignment and ordering of vector elements for single instruction multiple data processing
MIPS TECH INC12 citations81
SILICON GRAPHICS INC
7 patentsUS5574877ANov 12, 1996
TLB with two physical pages per virtual tag
SILICON GRAPHICS INC60 citations96
US5568630AOct 22, 1996
Backward-compatible computer architecture with extended word size and address space
SILICON GRAPHICS INC65 citations94
US5420992AMay 30, 1995
Backward-compatible computer architecture with extended word size and address space
SILICON GRAPHICS INC65 citations94
US5398328AMar 14, 1995
System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders
SILICON GRAPHICS INC82 citations94
US5479630ADec 26, 1995
Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same
SILICON GRAPHICS INC35 citations93
US5696958ADec 9, 1997
Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
SILICON GRAPHICS INC47 citations92
US5572713ANov 5, 1996
System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders
SILICON GRAPHICS INC36 citations90
KILLIAN EARL A
2 patentsUS8924898B2Dec 30, 2014
System and method of designing instruction extensions to supplement an existing processor instruction set architecture
KILLIAN EARL A16 citations90
US8875068B2Oct 28, 2014
System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions
KILLIAN EARL A4 citations82