Inventor
WIK THOMAS R
US18 patents
⚠️ This page may combine multiple inventors who share the name “WIK THOMAS R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
15 patentsUS5784328AJul 21, 1998
Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
LSI LOGIC CORP209 citations98
US5987632ANov 16, 1999
Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations
LSI LOGIC CORP106 citations97
US5982659ANov 9, 1999
Memory cell capable of storing more than two logic states by using different via resistances
LSI LOGIC CORP128 citations97
US5796650AAug 18, 1998
Memory circuit including write control unit wherein subthreshold leakage may be reduced
LSI LOGIC CORP107 citations94
US6370078B1Apr 9, 2002
Way to compensate the effect of coupling between bitlines in a multi-port memories
LSI LOGIC CORP22 citations92
US6233197B1May 15, 2001
Multi-port semiconductor memory and compiler having capacitance compensation
LSI LOGIC CORP21 citations92
US6137716AOct 24, 2000
Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell
LSI LOGIC CORP18 citations92
US5867423AFeb 2, 1999
Memory circuit and method for multivalued logic storage by process variations
LSI LOGIC CORP25 citations92
US5808932ASep 15, 1998
Memory system which enables storage and retrieval of more than two states in a memory cell
LSI LOGIC CORP39 citations92
US5761110AJun 2, 1998
Memory cell capable of storing more than two logic states by using programmable resistances
LSI LOGIC CORP34 citations92
US6507524B1Jan 14, 2003
Integrated circuit memory having column redundancy
LSI LOGIC CORP19 citations90
US5847990ADec 8, 1998
Ram cell capable of storing 3 logic states
LSI LOGIC CORP19 citations83
US5841695ANov 24, 1998
Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell
LSI LOGIC CORP11 citations73
US5903505AMay 11, 1999
Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions
LSI LOGIC CORP9 citations68
US6018480AJan 25, 2000
Method and system which permits logic signal routing over on-chip memories
LSI LOGIC CORP9 citations66