Inventor
MARTELL ROBERT W
US24 patents
⚠️ This page may combine multiple inventors who share the name “MARTELL ROBERT W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
17 patentsUS5761476AJun 2, 1998
Non-clocked early read for back-to-back scheduling of instructions
INTEL CORP114 citations98
US5555432ASep 10, 1996
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
INTEL CORP108 citations98
US5751942AMay 12, 1998
Trace event detection during trace enable transitions
INTEL CORP106 citations96
US5519864AMay 21, 1996
Method and apparatus for scheduling the dispatch of instructions from a reservation station
INTEL CORP65 citations96
US5809325ASep 15, 1998
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
INTEL CORP44 citations95
US5778210AJul 7, 1998
Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
INTEL CORP105 citations95
US6393550B1May 21, 2002
Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
INTEL CORP50 citations93
US6101597AAug 8, 2000
Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
INTEL CORP27 citations93
US5604878AFeb 18, 1997
Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
INTEL CORP33 citations93
US5553256ASep 3, 1996
Apparatus for pipeline streamlining where resources are immediate or certainly retired
INTEL CORP49 citations93
US5546597AAug 13, 1996
Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
INTEL CORP51 citations93
US5842036ANov 24, 1998
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
INTEL CORP27 citations92
US5826109AOct 20, 1998
Method and apparatus for performing multiple load operations to the same memory location in a computer system
INTEL CORP49 citations92
US5684971ANov 4, 1997
Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions
INTEL CORP29 citations89
US7208402B2Apr 24, 2007
Method and apparatus for improved power routing
INTEL CORP10 citations84
US5813037ASep 22, 1998
Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism
INTEL CORP19 citations82
US7180195B2Feb 20, 2007
Method and apparatus for improved power routing
INTEL CORP3 citations63
MARTELL ROBERT W
3 patentsUS8553055B1Oct 8, 2013
Thermal printer operable to selectively control the delivery of energy to a print head of the printer and method
MARTELL ROBERT W24 citations87
US8482586B1Jul 9, 2013
Thermal printer operable to selectively print sub-blocks of print data and method
MARTELL ROBERT W5 citations65
US8477162B1Jul 2, 2013
Thermal printer with static electricity discharger
MARTELL ROBERT W5 citations65