Inventor
ROBERDS BRIAN
US20 patents
⚠️ This page may combine multiple inventors who share the name “ROBERDS BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS6653700B2Nov 25, 2003
Transistor structure and method of fabrication
INTEL CORP144 citations99
US6563152B2May 13, 2003
Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
INTEL CORP172 citations99
US6362082B1Mar 26, 2002
Methodology for control of short channel effects in MOS transistors
INTEL CORP309 citations99
US6281532B1Aug 28, 2001
Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
INTEL CORP460 citations99
US6228694B1May 8, 2001
Method of increasing the mobility of MOS transistors by use of localized stress regions
INTEL CORP433 citations99
US6740913B2May 25, 2004
MOS transistor using mechanical stress to control short channel effects
INTEL CORP96 citations98
US6620713B2Sep 16, 2003
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
INTEL CORP80 citations98
US6952040B2Oct 4, 2005
Transistor structure and method of fabrication
INTEL CORP45 citations96
US6399973B1Jun 4, 2002
Technique to produce isolated junctions by forming an insulation layer
INTEL CORP51 citations96
US6815310B2Nov 9, 2004
Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
INTEL CORP26 citations92
US6261878B1Jul 17, 2001
Integrated circuit with dynamic threshold voltage
INTEL CORP37 citations92
US6656822B2Dec 2, 2003
Method for reduced capacitance interconnect system using gaseous implants into the ILD
INTEL CORP39 citations89
US6638835B2Oct 28, 2003
Method for bonding and debonding films using a high-temperature polymer
INTEL CORP16 citations79
US6809017B2Oct 26, 2004
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
INTEL CORP8 citations74
US6518109B2Feb 11, 2003
Technique to produce isolated junctions by forming an insulation layer
INTEL CORP12 citations74
US6642133B2Nov 4, 2003
Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
INTEL CORP12 citations68
US6489655B2Dec 3, 2002
Integrated circuit with dynamic threshold voltage
INTEL CORP5 citations63
US6873013B2Mar 29, 2005
Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
INTEL CORP0 citations47