Inventor

DOKUMACI OMER H

US88 patents

⚠️ This page may combine multiple inventors who share the name “DOKUMACI OMER H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOKUMACI OMER H

IBM

Silicon device on Si:C-OI and SGOI and method of manufacture

Strained finFETs and method of manufacture

Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS

Structure and method to improve channel mobility by gate electrode stress modification

Stress inducing spacers

Transistor having high mobility channel and methods

Isolation structures for imposing stress patterns

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

Backgated FinFET having different oxide thicknesses

Method and structure for improved MOSFETs using poly/silicide gate height control

MOSFET performance improvement using deformation in SOI structure

Silicide proximity structures for CMOS device performance improvements

MOS transistor

Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation

Embedded stressed nitride liners for CMOS performance improvement

Dual stressed SOI substrates

Strained Si on multiple materials for bulk or SOI substrates

High performance FET with laterally thin extension

Methods to improve the SiGe heterojunction bipolar device performance

Method and structure for improved MOSFETs using poly/silicide gate height control

Method of manufacturing strained dislocation-free channels for CMOS

Nanocircuit and self-correcting etching method for fabricating same

Strained silicon on relaxed sige film with uniform misfit dislocation density

Ultra-thin channel device with raised source and drain and solid source extension doping

Damascene method for improved MOS transistor

Structure and method to preserve STI during etching

Method of protecting semiconductor areas while exposing a gate

Method for forming high performance CMOS devices with elevated sidewall spacers

Self-aligned planar double-gate transistor structure

Stress inducing spacers

Self-aligned planar double-gate process by self-aligned oxidation

NFETs using gate induced stress modulation

CMOS performance enhancement using localized voids and extended defects

Self-aligned planar double-gate process by amorphization

High performance logic and high density embedded dram with borderless contact and antispacer

Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS

Method of improving gate activation by employing atomic oxygen enhanced oxidation

Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

Anti-halo compensation

Halo-first ultra-thin SOI FET for superior short channel control

Methods to improve the SiGe heterojunction bipolar device performance

Dual stressed SOI substrates

High performance FET with laterally thin extension

Method of making thermally stable planarizing films

Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation

High performance logic and high density embedded dram with borderless contact and antispacer

Anti-spacer structure for self-aligned independent gate implantation

Strained silicon on relaxed sige film with uniform misfit dislocation density

Strained dislocation-free channels for CMOS and method of manufacture

CHIDAMBARRAO DURESETI

Silicon device on Si:C-OI and SGOI and method of manufacture