Inventor
MADAN SUDHIR KUMAR
US8 patents
Patents
8 patentsUS7443708B2Oct 28, 2008
Low resistance plate line bus architecture
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US7133304B2Nov 7, 2006
Method and apparatus to reduce storage node disturbance in ferroelectric memory
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US7193880B2Mar 20, 2007
Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
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US7630257B2Dec 8, 2009
Methods and systems for accessing memory
TEXAS INSTRUMENTS INC13 citations84
US7561458B2Jul 14, 2009
Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory
TEXAS INSTRUMENTS INC11 citations82
US7301795B2Nov 27, 2007
Accelerated low power fatigue testing of FRAM
TEXAS INSTRUMENTS INC6 citations72
US7200027B2Apr 3, 2007
Ferroelectric memory reference generator systems using staging capacitors
TEXAS INSTRUMENTS INC7 citations72
US7009864B2Mar 7, 2006
Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
TEXAS INSTRUMENTS INC4 citations61