Inventor
BEUKEMA BRUCE L
US19 patents
⚠️ This page may combine multiple inventors who share the name “BEUKEMA BRUCE L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS7895383B2Feb 22, 2011
Event queue in a logical partition
IBM13 citations92
US7366813B2Apr 29, 2008
Event queue in a logical partition
IBM21 citations92
US7362705B2Apr 22, 2008
Dynamic load-based credit distribution
IBM15 citations92
US7290077B2Oct 30, 2007
Event queue structure and method
IBM29 citations92
US5584033ADec 10, 1996
Apparatus and method for burst data transfer employing a pause at fixed data intervals
IBM28 citations92
US5146605ASep 8, 1992
Direct control facility for multiprocessor network
IBM43 citations87
US7548964B2Jun 16, 2009
Performance counters for virtualized network interfaces of communications networks
IBM8 citations84
US5586265ADec 17, 1996
Priority arbitrating interface for a plurality of shared subsystems coupled to a plurality of system processing devices for selective association of subsystem to processing device
IBM10 citations73
US5506964AApr 9, 1996
System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system
IBM15 citations73
US5081624AJan 14, 1992
Fault-tolerant serial attachment of remote high-speed i/o busses
IBM14 citations73
US7409558B2Aug 5, 2008
Low-latency data decryption interface
IBM7 citations71
US7660247B2Feb 9, 2010
Dynamic load-based credit distribution
IBM3 citations63
US7496753B2Feb 24, 2009
Data encryption interface for reducing encrypt latency impact on standard traffic
IBM5 citations63
US7948894B2May 24, 2011
Data flow control for simultaneous packet reception
IBM2 citations62
US7385925B2Jun 10, 2008
Data flow control method for simultaneous packet reception
IBM4 citations62
US7970952B2Jun 28, 2011
Performance counters for virtualized network interfaces of communications networks
IBM0 citations52
US7840757B2Nov 23, 2010
Method and apparatus for providing high speed memory for a processing unit
IBM0 citations52
US7577794B2Aug 18, 2009
Low latency coherency protocol for a multi-chip multiprocessor system
IBM1 citations52