Inventor

CAMERON KELLY BRIAN

US98 patents

⚠️ This page may combine multiple inventors who share the name “CAMERON KELLY BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAMERON KELLY BRIAN

BROADCOM CORP

Stopping and/or reducing oscillations in low density parity check (LDPC) decoding

LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing

Variable modulation with LDPC (low density parity check) coding

Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses

LDPC (low density parity check) coded signal decoding using parallel and simultaneous bit node and check node processing

LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices

Overlapping sub-matrix based LDPC (low density parity check) decoder

Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices

LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems

AMP (accelerated message passing) decoder adapted for LDPC (low density parity check) codes

System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave

Decoder design adaptable to decode coded signals using min* or max* processing

LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance

Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps

Interleaver for iterative decoder

LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance

Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph

Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals

Symbol by symbol variable constellation type and/or mapping capable communication device

Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps

Efficient LDPC code decoding with new minus operator in a finite precision radix system

Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses

Symbol mapping for binary coding

Multiple input multiple output wireless local area network communications

True bit level decoding of TTCM (turbo trellis code modulation) of variable rates and signal constellations

Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices

Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices

Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders

Construction of irregular LDPC (low density parity check) codes using RS (Reed-Solomon) codes or GRS (generalized Reed-Solomon) code

Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder

LDPC (Low Density Parity Check) coded modulation hybrid decoding

Efficient design to implement min**/min**- or max**/max**- functions in LDPC (low density parity check) decoders

Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density Parity Check) coded modulation

Efficient design to implement LDPC (Low Density Parity Check) decoder

Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder

IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals

Fast min*- or max*-circuit in LDPC (low density parity check) decoder

Decoding LDPC (low density parity check) code with new operators based on min* operator

8 PSK rotationally invariant turbo trellis coded modulation without parallel transitions

Communication decoder employing single trellis to support multiple code rates and/or multiple modulations

16 QAM and 16 APSK TTCM (Turbo Trellis Coded Modulation) with minimum bandwidth efficiency of 3 bit/s/Hz using a rate 2/4 constituent encoder

Amplifying magnitude metric of received signals during iterative decoding of LDPC (Low Density Parity Check) code and LDPC coded modulation

Metric calculation design for variable code rate decoding of broadband trellis, TCM, or TTCM

LDPC (low density parity check) code size adjustment by shortening and puncturing

SHEN BA-ZHONG

Variable modulation with LDPC (low density parity check) coding

LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices

LDPC (low density parity check) code size adjustment by shortening and puncturing

LDPC (low density parity check) coding and interleaving implemented in MIMO communication systems

Flexible rate matching

LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices

Efficient design to implement min/min- or max/max- functions in LDPC (low density parity check) decoders

Fast min- or max-circuit in LDPC (low density parity check) decoder