Inventor
SUEKI SATORU
JP12 patents
⚠️ This page may combine multiple inventors who share the name “SUEKI SATORU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEADWAY TECHNOLOGIES INC
7 patentsUS7863095B2Jan 4, 2011
Method of manufacturing layered chip package
HEADWAY TECHNOLOGIES INC233 citations99
US7968374B2Jun 28, 2011
Layered chip package with wiring on the side surfaces
HEADWAY TECHNOLOGIES INC17 citations92
US7767494B2Aug 3, 2010
Method of manufacturing layered chip package
HEADWAY TECHNOLOGIES INC24 citations92
US7745259B2Jun 29, 2010
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC24 citations92
US7964976B2Jun 21, 2011
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC8 citations84
US7868442B2Jan 11, 2011
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC10 citations84
US7846772B2Dec 7, 2010
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC6 citations74
SASAKI YOSHITAKA
4 patentsUS8154116B2Apr 10, 2012
Layered chip package with heat sink
SASAKI YOSHITAKA11 citations84
US8134229B2Mar 13, 2012
Layered chip package
SASAKI YOSHITAKA5 citations63
US8324741B2Dec 4, 2012
Layered chip package with wiring on the side surfaces
SASAKI YOSHITAKA3 citations62
US8513034B2Aug 20, 2013
Method of manufacturing layered chip package
SASAKI YOSHITAKA0 citations52