Inventor
TERAHARA MASANORI
JP25 patents
⚠️ This page may combine multiple inventors who share the name “TERAHARA MASANORI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FUJITSU SEMICONDUCTOR LTD
7 patentsUS7947567B2May 24, 2011
Method of fabricating a semiconductor device with reduced oxide film variation
FUJITSU SEMICONDUCTOR LTD5 citations62
US7846792B2Dec 7, 2010
Method for manufacturing semiconductor device and semiconductor device manufacturing system
FUJITSU SEMICONDUCTOR LTD3 citations62
US8043917B2Oct 25, 2011
Method for manufacturing semiconductor device
FUJITSU SEMICONDUCTOR LTD0 citations51
US8847282B2Sep 30, 2014
Semiconductor device and fabrication method
FUJITSU SEMICONDUCTOR LTD0 citations50
US8835327B2Sep 16, 2014
Method of manufacturing semiconductor device
FUJITSU SEMICONDUCTOR LTD0 citations50
US8039358B2Oct 18, 2011
Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted
FUJITSU SEMICONDUCTOR LTD0 citations42
US9117675B2Aug 25, 2015
Semiconductor device production method
FUJITSU SEMICONDUCTOR LTD0 citations41
SANDISK TECHNOLOGIES INC
5 patentsUS9548313B2Jan 17, 2017
Method of making a monolithic three dimensional NAND string using a select gate etch stop layer
SANDISK TECHNOLOGIES INC25 citations94
US9437606B2Sep 6, 2016
Method of making a three-dimensional memory array with etch stop
SANDISK TECHNOLOGIES INC38 citations94
US9099496B2Aug 4, 2015
Method of forming an active area with floating gate negative offset profile in FG NAND memory
SANDISK TECHNOLOGIES INC31 citations94
US9530788B2Dec 27, 2016
Metallic etch stop layer in a three-dimensional memory structure
SANDISK TECHNOLOGIES INC24 citations91
US9093480B2Jul 28, 2015
Spacer passivation for high aspect ratio etching of multilayer stacks for three dimensional NAND device
SANDISK TECHNOLOGIES INC16 citations84
SANDISK TECHNOLOGIES LLC
4 patentsUS10014316B2Jul 3, 2018
Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof
SANDISK TECHNOLOGIES LLC35 citations93
US11282783B2Mar 22, 2022
Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same
SANDISK TECHNOLOGIES LLC7 citations85
US10872857B1Dec 22, 2020
Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same
SANDISK TECHNOLOGIES LLC17 citations84
US11398497B2Jul 26, 2022
Three-dimensional memory device containing auxiliary support pillar structures and method of making the same
SANDISK TECHNOLOGIES LLC5 citations72
FUJITSU MICROELECTRONICS LTD
3 patentsUS7601576B2Oct 13, 2009
Method for fabricating semiconductor device
FUJITSU MICROELECTRONICS LTD24 citations91
US7541120B2Jun 2, 2009
Manufacturing method of semiconductor device
FUJITSU MICROELECTRONICS LTD2 citations62
US7501686B2Mar 10, 2009
Semiconductor device and method for manufacturing the same
FUJITSU MICROELECTRONICS LTD6 citations62
FUJITSU LTD
3 patentsUS7701016B2Apr 20, 2010
Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method
FUJITSU LTD7 citations72
US6979610B2Dec 27, 2005
Semiconductor device fabrication method
FUJITSU LTD2 citations63
US7951686B2May 31, 2011
Method of manufacturing semiconductor device having device characteristics improved by straining surface of active region
FUJITSU LTD4 citations61