Inventor

TRAVIS EDWARD O

US58 patents

⚠️ This page may combine multiple inventors who share the name “TRAVIS EDWARD O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAVIS EDWARD O

FREESCALE SEMICONDUCTOR INC

Semiconductor device for reducing photovolatic current

Die level metal density gradient for improved flip chip package reliability

Teleconferencing environment having auditory and visual cues

Method for forming an integrated circuit having a programmable fuse

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

3D device packaging using through-substrate posts

Method of implementing polishing uniformity and modifying layout data

Method of implementing polishing uniformity and modifying layout data

EPI T-gate structure for CoSi2 extendibility

Spacer T-gate structure for CoSi2 extendibility

Semiconductor device for reducing photovolatic current

Primitive cell method for front end physical design

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

Method and apparatus for indicating directionality in integrated circuit manufacturing

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Semiconductor device with embedded heat spreading

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

Semiconductor device with vias on a bridge connecting two buses

Integrated assist features for epitaxial growth

MOTOROLA INC

Method of forming an integrated circuit device using dummy features and structure thereof

Semiconductor device and a process for designing a mask

Method of making a semiconductor device having an improved metallization structure

Method for providing a dummy feature and structure thereof

Semiconductor device, a process for a semiconductor device, and a process for making a masking database

Semiconductor device and process for generating an etch pattern

Method for adding features to a design layout and process for designing a mask

Process for forming a semiconductor device having a bond pad

Semiconductor device having a bond pad

Selective sizing of features to compensate for resist thickness variations in semiconductor devices

Semiconductor tiling structure and method of formation

REBER DOUGLAS M

Method for forming an electrical connection between metal layers

Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules

Method and system for derived layer checking for semiconductor device design

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit

Thin beam deposited fuse

Stress migration mitigation

Method for forming an electrical connection between metal layers

Semiconductor device with vias on a bridge connecting two buses

Method for forming an electrical connection between metal layers

SHROFF MEHUL D

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Device matching tool and methods thereof

Via placement and electronic circuit design processing method and electronic circuit design utilizing same

Capping layer interface interruption for stress migration mitigation

Multi-layer process-induced damage tracking and remediation

Mismatch verification device and methods thereof

TRAVIS EDWARD O

Integrated circuit design using pre-marked circuit element object library

Semiconductor device with embedded heat spreading

Semiconductor device with heat dissipation