Inventor

PHAN LAN D

US22 patents

⚠️ This page may combine multiple inventors who share the name “PHAN LAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PHAN LAN D

WESTERN DIGITAL TECH INC

System and method for reducing contentions in solid-state memory access

System and method for performing data retention in solid-state memory utilizing copy commands and usage data

System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata

System and method for performing data retention in solid-state memory using an LRU list

System data storage mechanism providing coherency and segmented data loading

System and method for managing access requests to a memory storage subsystem

System and method for managing access requests to a memory storage subsystem

System data storage mechanism providing coherency and segmented data loading

System data storage mechanism providing coherency and segmented data loading

System and method for managing execution of internal commands and host commands in a solid-state memory

KANG HO-FAN

System and method for managing execution of internal commands and host commands in a solid-state memory

System and method for improving data integrity and power-on performance in storage devices

System and method for enhancing processing of memory access requests

CALL MATTHEW

System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata

Solid-state drive with reduced power up time

Mapping table for improving write operation efficiency

SYU MEI-MAN L

System and method for reducing contentions in solid-state memory access

System and method for performing data retention in solid-state memory using copy commands and validity and usage data

LO JERRY

Managing wear leveling and garbage collection operations in a solid-state memory using linked lists

System data storage mechanism providing coherency and segmented data loading

PHAN LAN D

Non-volatile semiconductor memory segregating sequential data during garbage collection to reduce write amplification

System and method for multistage processing in a memory storage subsystem