Inventor
CHILAPPAGARI SHASHI KIRAN
US41 patents
⚠️ This page may combine multiple inventors who share the name “CHILAPPAGARI SHASHI KIRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
18 patentsUS9153336B1Oct 6, 2015
Decoder parameter estimation using multiple memory reads
MARVELL INT LTD26 citations93
US9755665B1Sep 5, 2017
Systems and methods for an iterative decoding scheme
MARVELL INT LTD20 citations92
US9577675B1Feb 21, 2017
System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures
MARVELL INT LTD19 citations92
US9614548B1Apr 4, 2017
Systems and methods for hybrid message passing and bit flipping decoding of LDPC codes
MARVELL INT LTD8 citations84
US9564931B1Feb 7, 2017
Systems and methods for using decoders of different complexity in a hybrid decoder architecture
MARVELL INT LTD15 citations84
US9548764B1Jan 17, 2017
Memory efficient decoders for low-density parity-check codes
MARVELL INT LTD12 citations84
US9537508B1Jan 3, 2017
Systems and methods for decoding cascade LDPC codes
MARVELL INT LTD7 citations84
US9437320B1Sep 6, 2016
Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference
MARVELL INT LTD14 citations84
US8984378B1Mar 17, 2015
Systems and methods for performing multi-state bit flipping in an LDPC decoder
MARVELL INT LTD11 citations84
US10200064B1Feb 5, 2019
Systems and method for bit-flipping decoders with partial-column processing, ordering and scheduling
MARVELL INT LTD9 citations82
US10790857B1Sep 29, 2020
Systems and methods for using decoders of different complexity in a hybrid decoder architecture
MARVELL INT LTD2 citations73
US10587288B1Mar 10, 2020
Systems and methods for iterative coding of product codes in nand FLASH controllers
MARVELL INT LTD2 citations73
US10411735B1Sep 10, 2019
Systems and methods for an iterative decoding scheme
MARVELL INT LTD4 citations73
US10153786B1Dec 11, 2018
Iterative decoder with dynamically-variable performance
MARVELL INT LTD4 citations73
US10365966B1Jul 30, 2019
Methods and systems for wordline based encoding and decoding in NAND flash
MARVELL INT LTD2 citations71
US10038456B1Jul 31, 2018
Decoders with look ahead logic
MARVELL INT LTD5 citations71
US8943381B1Jan 27, 2015
Systems and methods for performing bit flipping in an LDPC decoder
MARVELL INT LTD3 citations63
US10084480B1Sep 25, 2018
Systems and methods for decoding cascade LDPC codes
MARVELL INT LTD0 citations52
MARVELL WORLD TRADE LTD
11 patentsUS9385753B2Jul 5, 2016
Systems and methods for bit flipping decoding with reliability inputs
MARVELL WORLD TRADE LTD9 citations84
US8913437B2Dec 16, 2014
Inter-cell interference cancellation
MARVELL WORLD TRADE LTD11 citations84
US8885415B2Nov 11, 2014
Determining optimal reference voltages for progressive reads in flash memory systems
MARVELL WORLD TRADE LTD8 citations84
US9369152B2Jun 14, 2016
Systems and methods for decoding with late reliability information
MARVELL WORLD TRADE LTD4 citations73
US9323611B2Apr 26, 2016
Systems and methods for multi-stage soft input decoding
MARVELL WORLD TRADE LTD6 citations73
US9203432B2Dec 1, 2015
Symbol flipping decoders of non-binary low-density parity check (LDPC) codes
MARVELL WORLD TRADE LTD3 citations63
US9467170B2Oct 11, 2016
NAND flash memory systems with efficient soft information interface
MARVELL WORLD TRADE LTD0 citations52
US9183942B2Nov 10, 2015
Inter-cell interference cancellation
MARVELL WORLD TRADE LTD0 citations52
US9153323B2Oct 6, 2015
Systems and methods for generating soft information in NAND flash
MARVELL WORLD TRADE LTD0 citations52
US9152558B2Oct 6, 2015
Mapping different portions of data to different pages of multi-level non-volatile memory
MARVELL WORLD TRADE LTD0 citations52
US9379738B2Jun 28, 2016
Systems and methods for decoding using partial reliability information
MARVELL WORLD TRADE LTD0 citations41
CHILAPPAGARI SHASHI KIRAN
5 patentsUS8531888B2Sep 10, 2013
Determining optimal reference voltages for progressive reads in flash memory systems
CHILAPPAGARI SHASHI KIRAN44 citations93
US8694868B1Apr 8, 2014
Systems and methods for performing multi-state bit flipping in an LDPC decoder
CHILAPPAGARI SHASHI KIRAN10 citations84
US9009574B2Apr 14, 2015
Identification and mitigation of hard errors in memory systems
CHILAPPAGARI SHASHI KIRAN5 citations73
US8875000B2Oct 28, 2014
Methods and systems systems for encoding and decoding in trellis coded modulation systems
CHILAPPAGARI SHASHI KIRAN2 citations62
US8825945B2Sep 2, 2014
Mapping different portions of data to different pages of multi-level non-volatile memory
CHILAPPAGARI SHASHI KIRAN2 citations62