Inventor

DUTTA DEEPANSHU

US189 patents

⚠️ This page may combine multiple inventors who share the name “DUTTA DEEPANSHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUTTA DEEPANSHU

SANDISK TECHNOLOGIES LLC

First read countermeasures in memory

Countermeasure for reducing peak current during program operation under first read condition

Countermeasures for first read issue

Negative voltage wordline methods and systems

Read scrub with adaptive counter management

Sub-block mode for non-volatile memory

Multi-state program using controlled weak boosting for non-volatile memory

State dependent sensing for wordline interference correction

No-verify programming followed by short circuit test in memory device

Systems and methods for dual-pulse programming

Read operation for non-volatile memory with compensation for adjacent wordline

Row dependent sensing in nonvolatile memory

Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof

Managing bit-line settling time in non-volatile memory

Non-volatile memory with countermeasure for select gate disturb

Non-volatile memory with countermeasure for program disturb including delayed ramp down during program verify

Fast detection of defective memory block to prevent neighbor plane disturb

Programming process combining adaptive verify with normal and slow programming speeds in a memory device

Dynamic 1-tier scan for high performance 3D NAND

Interleaved program and verify in non-volatile memory

Non-volatile memory with countermeasure for program disturb including purge during precharge

Non-volatile memory with countermeasure for program disturb including spike during boosting

Peak current suppression

Asymmetric voltage ramp rate control

Overheat prevention for annealing non-volatile memory

SANDISK TECHNOLOGIES INC

Smart skip verify mode for programming a memory device

Adaptive determination of program parameter using program of erase rate

On chip dynamic read level scan and error detection for nonvolatile storage

Dynamic erase depth for improved endurance of non-volatile memory

Method and apparatus for program and erase of select gate transistors

On chip dynamic read for non-volatile storage

Compensating non-volatile storage using different pass voltages during program-verify and read

Controlling select gate voltage during erase to improve endurance in non-volatile memory

Multi-die programming with die-jumping induced periodic delays

Double verify method in multi-pass programming to suppress read noise

Double verify method with soft programming to suppress read noise

Double lockout in non-volatile memory

DUTTA DEEPANSHU

On chip dynamic read for non-volatile storage

Program temperature dependent read

Natural threshold voltage distribution compaction in non-volatile memory

Programming non-volatile memory with bit line voltage step up

Programming non-volatile memory with a reduced number of verify operations

Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory

SANDISK CORP

Multi-pass programming for memory using word line coupling

Programming algorithm to reduce disturb with minimal extra time penalty

Compensating for coupling during read operations in non-volatile storage

LUTZE JEFFREY W

Pair bit line programming to improve boost voltage clamping

LAI CHUN-HUNG

Selected word line dependent select gate voltage during program

OOWADA KEN

Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage

WESTERN DIGITAL TECH INC

Reducing post-read disturb in a nonvolatile memory device