Inventor

EISEN SUSAN E

US48 patents

⚠️ This page may combine multiple inventors who share the name “EISEN SUSAN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EISEN SUSAN E

IBM

Redistribution of architected states for a processor register file

Completion arbitration for more than two threads based on resource limitations

Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

Check pointing of accumulator register results in a microprocessor

Speculative execution of both paths of a weakly predicted branch instruction

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Logical register recovery within a processor

Fast mapper restore for flush in processor

Completion mechanism for a microprocessor instruction completion table

Thread transition management

Saving and restoring a transaction memory state

Instruction completion table containing entries that share instruction tags

Efficiently managing speculative finish tracking and error handling for load instructions

Method and apparatus for managing a speculative transaction in a processing unit

Logical register recovery within a processor

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Instruction dispatch routing

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Supporting speculative microprocessor instruction execution

System and handling of register data in processors

Routing instruction results to a register block of a subdivided register file based on register block utilization rate

Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry

Thread transition management

Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions

Thread transition management

Thread transition management

Prioritization of threads in a simultaneous multithreading processor core

Finish status reporting for a simultaneous multithreading processor using an instruction completion table

System and handling of register data in processors

Prioritized instructions in an instruction completion table of a simultaneous multithreading processor

Instruction completion table with ready-to-complete vector

Mechanism for completing atomic instructions in a microprocessor

Completion mechanism for a microprocessor instruction completion table

Mechanism to stop completions using stop codes in an instruction completion table

Speeding up younger store instruction execution after a sync instruction

Efficiently managing speculative finish tracking and error handling for load instructions

Executing system call vectored instructions in a multi-slice processor

Executing system call vectored instructions in a multi-slice processor

On-demand multi-tiered hang buster for SMT microprocessor

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor

Flush-recovery bandwidth in a processor

Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data

Operation of a multi-slice processor with history buffers storing transaction memory state information

ABERNATHY CHRISTOPHER M

Thread transition management

DOING RICHARD W

Tracking effective addresses in an out-of-order processor

BLAINEY ROBERT J

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

EISEN SUSAN E

Speeding up younger store instruction execution after a sync instruction