Inventor

HSU JEN-SHOU

TW23 patents

⚠️ This page may combine multiple inventors who share the name “HSU JEN-SHOU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU JEN-SHOU

ETRON TECHNOLOGY INC

Charge pump circuit for high voltage generation

Internal power management scheme for a memory chip in deep power down mode

Decoupling capacitor circuit

Internal power management scheme for a memory chip in deep power down mode

Charge pump circuit control system

Multiple power supplies for the driving circuit of local word line driver of DRAM

Speeding up the power-up procedure for low power RAM

Method for detecting erroneous word lines of a memory array and device thereof

Negative voltage generator

Calibrated built-in temperature sensor and calibration method thereof

Memory testing system and memory module thereof

Trigger circuit of a column redundant circuit and related column redundant device

ELITE SEMICONDUCTOR MEMORY TECH INC

Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit

Semiconductor memory device having compression test mode

Synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signal

Test system and device

ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC

Data first-in first-out (FIFO) circuit

Method and circuit for adaptive column-select line signal generation

Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device

Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuit

HSU JEN-SHOU

Semiconductor memory device and method of testing the same

Repairing circuit for memory circuit and method thereof and memory circuit using the same

ELITE SEMICONDUCTOR ESMT

Delay line circuit and phase interpolation module thereof